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CS0–
CS1–
DA2
Command block registers
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
X
Control block registers
0
1
1
0
1
1
Notes:
1.
The Data register for read or write operation can be accessed by 16 bit data bus (DATA0
to DATA15).
2.
The registers for read or write operation other than the Data registers can be accessed by
8 bit data bus (DATA0 to DATA7).
3.
When reading the Drive Address register, bit 7 is high-impedance state.
4.
The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector
Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.
Table 5.3
I/O registers
DA1
DA0
Read operation
0
0
Data
0
1
Error Register
1
0
Sector Count
1
1
Sector Number
0
0
Cylinder Low
0
1
Cylinder High
1
0
Device/Head
1
1
Status
X
X
(Invalid)
1
0
Alternate Status
1
1
—
C141-E110-02EN
I/O registers
Write operation
Data
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
(Invalid)
Device Control
—
Host I/O
address
X'1F0'
X'1F1'
X'1F2'
X'1F3'
X'1F4'
X'1F5'
X'1F6'
X'1F7'
—
X'3F6'
X'3F7'
5 - 7
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