Signal Assignment On The Connector; Signal Assignment On The Interface Connector - Fujitsu MPG3xxxAT Product Manual

5.1.2

Signal assignment on the connector

Table 5.2 shows the signal assignment on the interface connector.
Table 5.2
Pin No.
1 RESET–
3 DATA7
5 DATA6
7 DATA5
9 DATA4
11 DATA3
13 DATA2
15 DATA1
17 DATA0
19 GND
21 DMARQ
23 DIOW–, STOP
25 DIOR–, HDMARDY–, HSTROBE
27 IORDY, DDMARDY–, DSTROBE
29 DMACK–
31 INTRQ
33 DA1
35 DA0
37 CS0–
39 DASP–
[signal]
RESET–
DATA 0-15
DIOW–, STOP

Signal assignment on the interface connector

Signal
[I/O]
I Reset signal from the host. This signal is low active and is asserted
for a minimum of 25 s during power on. The device has a 10 k
pull-up resistor on this signal.
I/O Sixteen-bit bi-directional data bus between the host and the device.
These signals are used for data transfer
I DIOW– is the strobe signal asserted by the host to write device
registers or the data port.
DIOW– shall be negated by the host prior to initiation of an Ultra
DMA burst. STOP shall be negated by the host before data is
transferred in an Ultra DMA burst. Assertion of STOP by the host
during an Ultra DMA burst signals the termination of the Ultra
DMA burst.
C141-E110-02EN
Pin No. Signal
2 GND
4 DATA8
6 DATA9
8 DATA10
10 DATA11
12 DATA12
14 DATA13
16 DATA14
18 DATA15
20 (KEY)
22 GND
24 GND
26 GND
28 CSEL
30 GND
32 reserved
34 PDIAG–, CBLID–
36 DA2
38 CS1–
40 GND
[Description]
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