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If device 1 is present:
Both devices shall execute self-diagnosis.
The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.
If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall
append X'80' to its own diagnostic status.
The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device
1 does not generate an interrupt.)
A diagnostic status of the device 0 is read by the host system. When a diagnostic failure of
the device 1 is detected, the host system can read a status of the device 1 by setting the DV bit
(selecting the device 1).
When device 1 is not present:
The device 0 posts only the results of its own self-diagnosis.
The device 0 clears the BSY bit of the Status register, and generates an interrupt.
Table 5.7 lists the diagnostic code written in the Error register which is 8-bit code.
If the device 1 fails the self-diagnosis, the device 0 "ORs" X'80' with its own status and sets that
code to the Error register.
Code
X'00'
X'01'
X'02'
X'03'
X'04'
X'05'
X'06'
X'8x'
At command issuance (I/O registers setting contents)
1F7
(CM)
1
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
Table 5.7
Diagnostic code
Result of diagnostic
Mechanical failure
No error detected
Hardware error
Buffer failure
SRAM failure
SA read failure
Power ON calibration failure
Failure of device 1
0
0
1
0
DV
xx
xx
xx
xx
xx
C141-E110-02EN
0
0
0
xx
5 - 41
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