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Fujitsu MPA3017AT Product Manual

Fujitsu computer drive user manual
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MPA3017AT
MPA3026AT
MPA3035AT
MPA3043AT
MPA3052AT
DISK DRIVES
PRODUCT MANUAL
C141-E034-02EN

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Summary of Contents for Fujitsu MPA3017AT

  • Page 1 MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES PRODUCT MANUAL C141-E034-02EN...
  • Page 2 Edition Date published Jan., 1997 August, 1997 REVISION RECORD Revised contents Specification No.: C141-E034-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved. Copyright C141-E034-02EN 1997 FUJITSU LIMITED...
  • Page 3 This manual describes the MPA3017AT/MPA3026AT/MPA3035AT/MPA3043AT/MPA3052AT, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.
  • Page 4 Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.
  • Page 5 "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

  • Page 6: Table Of Contents

    CHAPTER 1 DEVICE OVERVIEW ... 1 - 1 Features... 1 - 1 1.1.1 Functions and performance... 1 - 1 1.1.2 Adaptability ... 1 - 2 1.1.3 Interface... 1 - 2 Device Specifications ... 1 - 4 1.2.1 Specifications summary ... 1 - 4 1.2.2 Model and product number...
  • Page 7 3.4.1 Location of setting jumpers ... 3 - 9 3.4.2 Factory default setting ... 3 - 10 3.4.3 Jumper configuration ... 3 - 10 CHAPTER 4 THEORY OF DEVICE OPERATION... 4 - 1 Outline ... 4 - 1 Subassemblies... 4 - 1 4.2.1 Disk...
  • Page 8 5.2.2 Command block registers ... 5 - 8 5.2.3 Control block registers... 5 - 13 Host Commands... 5 - 13 5.3.1 Command code and parameters ... 5 - 14 5.3.2 Command descriptions ... 5 - 16 5.3.3 Error posting... 5 - 54 Command Protocol ...
  • Page 9 6.3.1 Power save mode ... 6 - 8 6.3.2 Power commands... 6 - 10 Defect Management... 6 - 10 6.4.1 Spare area ... 6 - 11 6.4.2 Alternating defective sectors... 6 - 11 Read-Ahead Cache ... 6 - 13 6.5.1 Data buffer configuration...
  • Page 10 Current fluctuation (Typ.) at +5V when power is turned on... 1 - 7 Disk drive outerview... 2 - 1 Configuration of disk media heads ... 2 - 3 1 drive system configuration... 2 - 4 2 drives configuration ... 2 - 5 Dimensions ...
  • Page 11 Protocol for command abort ... 5 - 57 WRITE SECTOR(S) command protocol... 5 - 58 Protocol for the command execution without data transfer... 5 - 59 Normal DMA data transfer ... 5 - 61 Ultra DMA termination with pull-up or pull-down... 5 - 72 PIO data transfer timing...
  • Page 12 Specifications... 1 - 4 Model names and product numbers ... 1 - 5 Current and power dissipation ... 1 - 6 Environmental specifications... 1 - 8 Acoustic noise specification ... 1 - 8 Shock and vibration specification... 1 - 9 Surface temperature measurement points and standard values ...

  • Page 13: Chapter 1 Device Overview

    The disk drive can record up to 1,750 MB (formatted) on one disk using the (8/9) PRML recording method and 15 recording zone technology. The MPA3017AT, MPA3026AT, MPA3035AT, MPA3043AT and MPA3052AT have a formatted capacity of 1,750 MB, 2,625 MB, 3,500 MB, 4,375MB and 5,250MB respectively.

  • Page 14: Adaptability

    Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 10 ms (at read). 1.1.2 Adaptability Power save mode The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor.
  • Page 15 Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 18-byte ECC has improved buffer error correction for correctable data errors. Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media.

  • Page 16: Device Specifications

    Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. MPA3017AT Formatted Capacity (*1) 1750.00 MB Number of Heads Number of Cylinders (User + Alternate & SA) Bytes per Sector Recording Method Track Density Bit Density...

  • Page 17: Model And Product Number

    1.2.2 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Model Name Capacity (user area) MPA3017AT 1749.56 MB MPA3026AT 2624.86 MB MPA3035AT 3499.13 MB MPA3043AT 4374.42 MB MPA3052AT 5249.72 MB MPA3017AT 1749.56 MB MPA3026AT 2624.86 MB...

  • Page 18: Current And Power Dissipation

    Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Typical RMS current (*1) Mode of Operation +12 V Model 3017AT 3026AT 3035AT Spin up 1.3 A 1.5 A peak Idle (Ready) (*3) 0.120 A 0.155 A R/W (On Track) 0.130 A...

  • Page 19: Current Fluctuation (Typ.) At +5V When Power Is Turned On

    Current fluctuation (Typ.) at +5V when power is turned on Note: Maximum current is 1.5 A and is continuance is 1.5 seconds Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal.

  • Page 20: Environmental Specifications

    Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.4 Temperature • Operating • Non-operating • Thermal Gradient Humidity • Operating • Non-operating • Maximum Wet Bulb Altitude (relative to sea level) • Operating • Non-operating Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Sound Pressure •...

  • Page 21: Shock And Vibration

    Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Vibration (swept sine, one octave per minute) • Operating • Non-operating Shock (half-sine pulse, 11 ms duration) • Operating • Non-operating Reliability Mean time between failures (MTBF) The mean time between failures (MTBF) is 500,000 H or more (operation: 24 hours/day, 7 days/week).

  • Page 22: Error Rate

    Data assurance in the event of power failure Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment).

  • Page 23: Chapter 2 Device Configuration

    CHAPTER 2 DEVICE CONFIGURATION Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.1 Device Configuration System Configuration...
  • Page 24 The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. operations. MPA3017AT: 1 disk MPA3026AT: 2 disks MPA3035AT: 2 disks MPA3043AT: 3 disks...

  • Page 25: Configuration Of Disk Media Heads

    MPA3017 Model Spindle MPA3026AT Model Spindle MPA3043AT Model Spindle Figure 2.2 Spindle motor The disks are rotated by a direct drive Hall-less DC motor. Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat.

  • Page 26: System Configuration

    Air circulation system The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure.

  • Page 27: Drives Connection

    2.2.3 2 drives connection Host (Host adaptor) AT bus (Host interface) Note: When the drive that is not conformed to ATA is connected to the disk drive is above configuration, the operation is not guaranteed. Figure 2.4 HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment".

  • Page 28: Chapter 3 Installation Conditions

    CHAPTER 3 INSTALLATION CONDITIONS Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Dimensions Mounting Cable Connections Jumper Settings C141-E034-02EN 3 - 1...

  • Page 29: Dimensions

    Figure 3.1 Dimensions 3 - 2 C141-E034-02EN...

  • Page 30: Mounting

    Mounting Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. The mounting angle can vary ±5° from the horizontal. (a) Horizontal mounting Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground.

  • Page 31: Limitation Of Side-Mounting

    Figure 3.3 Bottom surface mounting Frame of system cabinet 4.5 or less Details of A Figure 3.4 3 - 4 Do not use this screw holes Limitation of side-mounting Side surface mounting Frame of system cabinet Screw 5.0 or less Details of B Mounting frame structure C141-E034-02EN...

  • Page 32: Surface Temperature Measurement Points

    Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.

  • Page 33: Service Area

    Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. - Mounting screw hole [P side] - Cable connection - Mode setting switches External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

  • Page 34: Cable Connections

    Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. Power supply connector (CN1) ATA interface connector (CN1) Power supply connector (CN1) Mode Setting Pins...

  • Page 35: Cable Connector Specifications

    Host system 3 - 8 Cable connector specifications Name Model FCN-707B040-AU/B FCN-707B040-AU/O 445-248-40 1-480424-0 60617-4 AWG 18 to 24 Power supply cable Disk Drive #0 Disk Drive #1 Figure 3.8 Cable connections C141-E034-02EN Manufacturer Fujitsu Fujitsu SPECTERS STRIP power supply...

  • Page 36: Power Supply Connector (Cn1)

    3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). (Viewed from cable side) Figure 3.9 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of the jumpers to select drive configuration and functions. Power supply connector...

  • Page 37: Factory Default Setting

    3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. Figure 3.11 Factory default setting 3.4.3 Jumper configuration Device type Master device (device #0) or slave device (device #1) is selected. (a) Master device Figure 3.12 Jumper setting of master or slave device Cable Select (CSEL) In Cable Select mode, the device can be configured either master device or slave device.

  • Page 38: Jumper Setting Of Cable Select

    CSEL connected to the interface Cable selection can be done by the special interface cable. Figure 3.13 Jumper setting of Cable Select Figures 3.14 and 3.15 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level.
  • Page 39 Special setting 1 (SP1) The number of cylinders reported by the IDENTIFY DEVICE command is selected. (a) Default mode Master Device Model No. of cylinders MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT (b) Special mode Master Device Model No. of cylinders MPA3017AT...

  • Page 40: Chapter 4 Theory Of Device Operation

    4.2.1 Disk The DE contains the disks with an outer diameter of 95 mm. The MPA3017AT has 1 disk, the MPA3026AT/MPA3035AT have 2 disks. MPA3043AT/MPA3052AT have 3 disks. The head contacts the disk each time the disk rotation stops; the life of the disk is 40,000 contacts or more.

  • Page 41: Head

    4.2.2 Head Figure 4.1 shows the read/write head structures. The MPA3017AT has 2 read/write heads, the MPA3026AT has 3, MPA3035AT has 4, MPA3043AT has 5, and MPA3052AT has 6. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed.

  • Page 42: Spindle

    4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm ±0.5%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.

  • Page 43: Circuit Configuration

    Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

  • Page 45: Power-On Sequence

    Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. successfully, the disk drive starts the spindle motor.

  • Page 46: Power-On Operation Sequence

    Power on Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. Self-diagnosis 2 • Data buffer write/read test Confirming spindle motor speed Release heads from actuator lock Initial on-track and read out of system information Execute self-calibration Drive ready state...

  • Page 47: Self-Calibration

    Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.

  • Page 48: Execution Timing Of Self-Calibration

    4.5.2 Execution timing of self-calibration Self-calibration is executed when: The power is turned on. The disk drive receives the RECALIBRATE command from the host. The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on.

  • Page 49: Read/Write Circuit

    Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mounted on the FPC.

  • Page 51: Read Circuit

    4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 52: Pr4 Signal Transfer

    Figure 4.6 PR4 signal transfer C141-E034-02EN 4 - 13...

  • Page 53: Time Base Generator Circuit

    Viterbi detection circuit The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence. Data separator circuit The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit.

  • Page 54: Servo Control

    Table 4.3 Write clock frequency and transfer rate of each zone Zone Cylinder 1788 Transfer rate 14.964 14.111 [MB/s] Zone Cylinder 4809 5120 5119 6107 Transfer rate 11.443 10.590 [MB/s] The MPU transfers the data transfer rate setup data (SDATA/SCLK) to the RDC that includes the time base generator circuit to change the data transfer rate.

  • Page 55: Servo Control Circuit

    4.7.1 Servo control circuit Figure 4.7 is the block diagram of the servo control circuit. The following describes the functions of the blocks: Servo burst Head capture Position Sense CSR: Current Sense Resistor VCM: Voice Coil Motor Figure 4.7 Microprocessor unit (MPU) The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to the reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operations of the MPU.

  • Page 56: Physical Sector Servo Configuration On Disk Surface

    c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value. Figure 4.8 Physical sector servo configuration on disk surface C141-E034-02EN 4 - 17...
  • Page 57 Servo burst capture circuit The four servo signals can be synchronously detected by the STROB signal, full-wave rectified integrated. A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.

  • Page 58: Data-Surface Servo Format

    4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

  • Page 59: Actuator Motor Control

    Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. Servo mark This area generates a timing for demodulating the gray code and position-demodulating the servo A to D by detecting the servo mark. Gray code (including index bit) This area is used as cylinder address.

  • Page 60: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control;...
  • Page 61 e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC.

  • Page 62: Chapter 5 Interface

    CHAPTER 5 INTERFACE Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing C141-E034-02EN 5 - 1...

  • Page 63: Physical Interface

    Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DMACK-: DMA ACKNOWLEDGE INTRQ : INTERRUPT REQUEST IOCS16-: IOCS 16 PDIAG- : PASSED DIAGNOSTIC IORDY : I/O CHANNEL READY DASP- : DEVICE ACTIVE/DEVICE 1 PRESENT DA 0-2: DEVICE ADDRESS CS0- : CHIP SELECT 0 CS1- : CHIP SELECT 1 RESET-: RESET...

  • Page 64: Signal Assignment On The Connector

    5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Pin No. RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DMARQ IOW–, STOP IOR–, HDMARDY–, HSTROBE IORDY, DDMARDY–, DSTROBE DMACK– INTRQ CS0–...
  • Page 65 [signal] [I/O] IOR–, HDMARDY–, HSTROBE INTRQ IOCS16– CS0– CS1– DA 0-2 – PIDAG– DASP– 5 - 4 [Description] IOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.
  • Page 66 [signal] [I/O] IORDY, This signal is negated to extend the host transfer cycle of any host DDMARDY–, register access (Read or Write) when the device is not ready to DSTROBE respond to a data transfer request. DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts.

  • Page 67: Logical Interface

    Logical Interface The device can operate for command execution in either address-specified mode; cylinder-head- sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.

  • Page 68: Command Block Registers

    CS0– CS1– Command block registers Control block registers Notes: The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15). The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).
  • Page 69 5.2.2 Command block registers Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

  • Page 70: Diagnostic Code

    [Diagnostic code] X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
  • Page 71 Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk- access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8.
  • Page 72 Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
  • Page 73 - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed.

  • Page 74: Host Commands

    5.2.3 Control block registers Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

  • Page 75: Command Code And Parameters

    5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written. Table 5.3 Command name READ SECTOR(S) READ MULTIPLE READ DMA READ VERIFY SECTOR(S) WRITE MULTIPLE WRITE DMA WRITE VERIFY WRITE SECTOR(S) RECALIBRATE SEEK...
  • Page 76 Table 5.3 Command name STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART Notes: FR : Features Register SC : Sector Count Register SN : Sector Number Register R: Retry at error 1 = Without retry 0 = with retry Y: Necessary to set parameters Y*: Necessary to set parameters under the LBA mode.

  • Page 77: Command Descriptions

    5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) WITH RETRY At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 78 Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).
  • Page 79 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ MULTIPLE (X'C4') This command operates similarly to the READ SECTOR(S) command.

  • Page 80: Execution Example Of Read Multiple Command

    Figure 5.2 shows an example of the execution of the READ MULTIPLE command. Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) Number of sectors in incomplete block = remainder of 9/4 =1 Command Issue Parameter...
  • Page 81 Note: If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register. READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion.
  • Page 82 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ VERIFY SECTOR(S) (X'40' or X'41') This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.
  • Page 83 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE SECTOR(S) (X'30' or X'31') This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count...
  • Page 84 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE MULTIPLE (X'C5') This command is similar to the WRITE SECTOR(S) command.
  • Page 85 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 86 1) Single word DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'12' by the SET FEATURES command 2) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 3) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents)
  • Page 87 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 with Retry R = 1 without Retry At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
  • Page 88 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers.
  • Page 89 (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.
  • Page 90 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E034-02EN 5 - 29...

  • Page 91: Information To Be Read By Identify Device Command

    X‘4000’ Support of command sets (fixed) 84-87 X‘00’ Reserved X‘0000’ or Ultra DMA modes *13 X‘0X07’ 5 - 30 Description MPA3017AT: X‘0D3E’ MPA3026AT: X‘13DE’ MPA3035AT: X‘1A7C’ MPA3043AT: X‘2352’ MPA3052AT: X‘2A62’ MPA3017AT: X‘0010’ MPA3026AT: X‘0010’ MPA3035AT: X‘0010’ MPA3043AT: X‘000F’ MPA3052AT: X‘000F’...
  • Page 92 *3 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified) *4 Word 27-46: Model number; ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20') One of three model numbers; MPA3017AT, MPA3026AT, MPA3035AT, MPA3043AT, MPA3052AT *5 Word 49: Capabilities Bit 15-14: Reserved Bit 13:...
  • Page 93 Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3) Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command Bit 15-9: Reserved Bit 8: Multiple sector transfer 1=Enable Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without interrupt supports 2, 4, 8, 16 and 32 sectors.
  • Page 94 (13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL)

  • Page 95: Features Register Values And Settable Modes

    Table 5.5 Features Register X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘55’ Disables read cache function. X‘66’ Disables the reverting to power-on default settings after software reset.
  • Page 96 The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value. However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting.
  • Page 97 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.
  • Page 98 (16) EXECUTE DEVICE DIAGNOSTIC (X'90') This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis. If device 1 is present: Both devices shall execute self-diagnosis.
  • Page 99 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 This register indicates X‘00’ in the LBA mode. (17) FORMAT TRACK (X'50') Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-byte format parameter transfer from the host system.
  • Page 100 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 with Retry R = 1 without Retry At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, this register indicates 01.
  • Page 101 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 with Retry R = 1 without Retry At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, this register indicates 01.
  • Page 102 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register.
  • Page 103 (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode.
  • Page 104 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 105 (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
  • Page 106 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (26) SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode.
  • Page 107 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers.
  • Page 108 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (28) SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.

  • Page 109: Features Register Values (Subcommands) And Functions

    Table 5.7 Features Register values (subcommands) and functions Features Resister X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
  • Page 110 The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers. If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life .

  • Page 111: Format Of Device Attribute Value Data

    The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Thresholds subcommand (FR register = D1h).

  • Page 112: Format Of Insurance Failure Threshold Value Data

    Table 5.9 Format of insurance failure threshold value data Byte Attribute 1 Threshold 1 (Threshold of attribute 1) Threshold 2 to threshold 30 Reserved Unique to vendor Check sum Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds.
  • Page 113 Attribute ID The attribute ID is defined as follows: Attribute ID (Indicates unused attribute data.) Reserved Reserved Spindle motor activation time Number of times the spindle motor is activated Number of alternative sectors Reserved Reserved Power-on time Number of retries made to activate the spindle motor Number of power-on-power-off times 13 to 199 (Reserved)
  • Page 114 Raw attribute value Raw attributes data is retained. Failure prediction capability flag Bit 0: The attribute value data is saved to a medium before the device enters power saving mode. Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation.

  • Page 115: Error Posting

    5.3.3 Error posting Table 5.10 lists the defined errors that are valid for each command. Table 5.10 Command code and parameters Command name Error register (X'1F1') READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE READ DMA WRITE DMA WRITE VERIFY READ VERIFY SECTOR(S) RECALIBRATE SEEK...

  • Page 116: Command Protocol

    Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to Commands can be executed only when the DRDY bit of the Status register is 1.

  • Page 117: Read Sector(S) Command Protocol

    Command Parameter write DRDY INTRQ Data transfer Expanded Command Min. 30 s (*1) INTRQ Data Reg. Selection Data IOR- Word IOCS16- *1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. Figure 5.3 Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer.

  • Page 118: Data Transferring Commands From Host To Device

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.

  • Page 119: Write Sector(S) Command Protocol

    c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register. e) The device clears the DRQ bit and sets the BSY bit. f) When the drive completes transferring the data of the sector, the device clears BSY bit and asserts INTRQ signal.

  • Page 120: Commands Without Data Transfer

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.

  • Page 121: Other Commands

    5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

  • Page 122: Normal Dma Data Transfer

    Command Parameter write DRDY INTRQ Data transfer Expanded [Single Word DMA transfer] DMARQ DMACK- IOR- or IOW- Word [Multiword DMA transfer] DMARQ DMACK- IOR- or IOW- Word Figure 5.7 • • • • • • • • • • • • • • •...

  • Page 123: Ultra Dma Feature Set

    Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).

  • Page 124: Phases Of Operation

    5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6.4 defines the specific timing requirements).
  • Page 125 11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within t has negated STOP and asserted HDMARDY-.
  • Page 126 The device shall stop generating DSTROBE edges within t HDMARDY-. If the host negates HDMARDY- within t edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t edge, then the host shall be prepared to receive zero, one or two additional data words.
  • Page 127 10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

  • Page 128: Ultra Dma Data Out Commands

    10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than t calculation on DD (15:0).
  • Page 129 9) The device shall assert DDMARDY- within t asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.
  • Page 130 The device shall pause an Ultra DMA burst by negating DDMARDY-. The host shall stop generating HSTROBE edges within t DDMARDY-. If the device negates DDMARDY- within t edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words.
  • Page 131 10) The device shall release DDMARDY- within t 11) The host shall neither negate STOP nor negate HSTROBE until at least t negating DMACK-. 12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t negating DMACK.

  • Page 132: Ultra Dma Crc Rules

    13) The host shall neither negate STOP nor HSTROBE until at least t DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

  • Page 133: Series Termination Required For Ultra Dma

    5.5.6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device. Table 5.11 Recommended series termination for Ultra DMA Signal DIOR-:HDMARDY-:HSTROBE...

  • Page 134: Timing

    Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. C141-E034-02EN 5 - 73...

  • Page 135: Pio Data Transfer Timing

    Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IOCS16- IORDY Symbol Timing parameter Cycle time Data register selection setup time for DIOR-/DIOW- Pulse width of DIOR-/DIOW- Recovery time of DIOR-/DIOW- Data setup time for DIOW- Data hold time for DIOW- Time from DIOR- assertion to read data available Data hold time for DIOR- Time from Data register selection to IOCS16- assertion...

  • Page 136: Single Word Dma Data Transfer

    5.6.2 Single word DMA data transfer Figure 5.10 show the single word DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Cycle time Delay time from DMACK assertion to DMARQ negation Pulse width of DIOR-/DIOW- Data setup time for DIOR- Data hold time for DIOR-...

  • Page 137: Multiword Data Transfer

    5.6.3 Multiword data transfer Figure 5.11 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Cycle time Delay time from DMACK assertion to DMARQ negation Pulse width of DIOR-/DIOW- Data setup time for DIOR- Data hold time for DIOR-...

  • Page 138: Ultra Dma Data Transfer

    5.6.4 Ultra DMA data transfer Figures 5.12 through 5.21 define the timings associated with all phases of Ultra DMA bursts. Table 5.12 contains the values for the timings for each of the Ultra DMA Modes. 5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.

  • Page 139: Ultra Dma Data Burst Timing Requirements

    5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirements NAME MODE 0 MODE 1 (in ns) (in ns) 5 - 78 MODE 2 (in ns) Cycle time (from STROBE edge to STROBE edge) Two cycle time (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) Data setup time (at recipient)
  • Page 140 NAME MODE 0 MODE 1 (in ns) (in ns) IORDYZ ZIORDY Notes: 1) t and t indicate sender -to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. t unlimited interlock, that has no maximum time value.

  • Page 141: Sustained Ultra Dma Data In Burst

    5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

  • Page 142: Host Pausing An Ultra Dma Data In Burst

    5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.

  • Page 143: Device Terminating An Ultra Dma Data In Burst

    5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.15 Device terminating an Ultra DMA data in burst 5 - 82 C141-E034-02EN...

  • Page 144: Host Terminating An Ultra Dma Data In Burst

    5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.16 Host terminating an Ultra DMA data in burst C141-E034-02EN 5 - 83...

  • Page 145: Initiating An Ultra Dma Data Out Burst

    5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.17 Initiating an Ultra DMA data out burst 5 - 84 C141-E034-02EN...

  • Page 146: Sustained Ultra Dma Data Out Burst

    5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

  • Page 147: Device Pausing An Ultra Dma Data Out Burst

    5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than after DDMARDY- is negated.

  • Page 148: Host Terminating An Ultra Dma Data Out Burst

    5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.20 Host terminating an Ultra DMA data out burst C141-E034-02EN 5 - 87...

  • Page 149: Device Terminating An Ultra Dma Data Out Burst

    5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.21 Device terminating an Ultra DMA data out burst 5 - 88 C141-E034-02EN...

  • Page 150: Power-On And Reset

    5.6.5 Power-on and reset Figure 5.22 shows power-on and reset (hardware and software reset) timing. Only master device is present Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. Master and slave devices are present (2-drives configuration) [Master device] DASP- [Slave device]...

  • Page 151: Operations

    CHAPTER 6 OPERATIONS Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. Device Response to the Reset Address Translation Power Save Defect Management...

  • Page 152: Response To Power-On

    6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 153: Response To Hardware Reset

    6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 154: Response To Software Reset

    6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 155: Response To Diagnostic Command

    6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.

  • Page 156: Address Translation

    Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.2.1 Default parameters In the logical to physical address translation, the logical cylinder, head, and sector addresses are...

  • Page 157: Logical Address

    6.2.2 Logical address CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent sector from the last sector of the current physical head address.

  • Page 158: Power Save

    LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. The logical address is advanced at the subsequent sector from the last sector of the current track. The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track.
  • Page 159 Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed. Active mode In this mode, all the electric circuit in the device are active or the device is under seek, read or write operation.

  • Page 160: Power Commands

    STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.

  • Page 161: Spare Area

    6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (11 cylinders/head) 2) Spare cylinder for alternative assignment: used for alternative assignment by automatic alternative assignment. (4 cylinders/head) 6.4.2 Alternating defective sectors The two alternating methods described below are available:...

  • Page 162: Alternate Cylinder Assignment

    Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0. Index Sector (physical) Cylinder 0...

  • Page 163: Read-Ahead Cache

    Automatic alternate assignment The device performs the automatic assignment at following case. 1) When ECC correction performance is increased during read error retry, a read error is recovered. Before automatic alternate assignment, the device performs rewriting the corrected data to the erred sector and rereading.

  • Page 164: Caching Operation

    6.5.2 Caching operation Caching operation is performed only at issuance of the following commands. The device transfers data from the data buffer to the host system at issuance of following command if following data exist in the data buffer. All sectors to be processed by the command A part of data including load sector to be processed by the command When a part of data to be processed exist in the data buffer, remaining data are read from the medium and are transferred to the host system.

  • Page 165: Usage Of Read Segment

    Invalidating caching data Caching data in the data buffer is invalidated in the following case. 1) Following command is issued to the same data block as caching data. WRITE SECTOR(S) WRITE DMA WRITE MULTIPLE 2) Command other than following commands is issued (all caching data are invalidated) READ SECTOR (S) READ DMA READ MULTIPLE...
  • Page 166 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the lead of segment. 2) Transfers the requested data that already read to the host system with reading the requested data from the disk media. Read-requested data 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation.
  • Page 167 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive starts the read-ahead operation. a. Sequential command just after non-sequential command When the previously executed read command is an non-sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive assumes the received command is a sequential command and performs the read-ahead operation after reading the requested data.
  • Page 168 The disk drive performs the read-ahead operation for all area of segment with overwriting the requested data. Finally, the cache data in the buffer is as follows. b. Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.
  • Page 169 After completion of data transfer of hit data, the disk drive performs the read-ahead operation for the data area of which the disk drive transferred hit data. Finally, the cache data in the buffer is as follows. Start LBA c. Non-sequential read command just after sequential read command When non-sequential read command is received after executing the sequential read command (read-ahead operation) and more than ten non-sequential read commands are received after that continuously, the read-ahead operation is stopped (refer to item (1)).
  • Page 170 1) In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command, the disk drive sets the HAP to the address of which the hit data is stored. Last position at previous read command Cache data 2) The disk drive transfers the requested data but does not perform the read-ahead operation.
  • Page 171 1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.

  • Page 172: Write Cache

    Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.
  • Page 173 At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state.
  • Page 174 FUJITSU LIMITED OEM Marketing 4-1-1, Kamikodanaka, Nakahara-Ku, Kawasaki, 211-88, Japan TEL: 044-754-8632 FAX: 044-754-8634 FUJITSU COMPUTER PRODUCTS OF AMERICA, INC. 2904 Orchard Parkway, San Jose, California 95134-2009, U.S.A. TEL: 1-408-432-6333 FAX: 1-408-432-3908 FUJITSU CANADA INC. 2800 Matheson Blvd. East, Mississauga, Toronto,...
  • Page 175 34-1-581-8125 FUJITSU AUSTRALIA LIMITED 475 Victoria Avenue, Chatswood, 2067 N.S.W, AUSTRALIA TEL: 61-2-410-4555 FAX: 61-2-411-8603, 8362 FUJITSU HONG KONG LIMITED Room 2521, Sun Hung Kai Centre, Harbour Road 30, HONG HONG TEL: 852-827-5780 FAX: 852-827-4724 FUJITSU KOREA LIMITED 6th Floor, Duk-Heung Bldg., 1328-10, Seocho-Dong, Seocho-Ku,...
  • Page 176 Thank you for your interest. Please send this sheet to one of the addresses in the left page. Is the material presented effectively? Sales Fully covered Operating What is your occupation? Very Poor Your Name & Return Address FUJITSU LIMITED Current Date Well Well Clean Illustrated Organized...

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