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9) The device shall assert DDMARDY- within t
asserting DMARQ and DDMARDY- the device shall not negate either signal until after the
first negation of HSTROBE by the host.
10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur
any time during Ultra DMA burst initiation.
11) To transfer the first word of data: the host shall negate HSTROBE no sooner than t
device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than t
the driving the first word of data onto DD (15:0).
5.5.4.2 The data out transfer
The following steps shall occur in the order they are listed unless otherwise specifically allowed
(see 5.6.3.8 and 5.6.3.2 for specific timing requirements):
1) The host shall drive a data word onto DD (15:0).
2) The host shall generate an HSTROBE edge to latch the new word no sooner than t
changing the state of DD (15:0). The host shall generate an HSTROBE edge more frequently
than t
for the selected Ultra DMA Mode. The host shall not generate two rising or falling
CYC
HSTROBE edges more frequently than 2 t
3) The host shall not change the state of DD (15:0) until at least t
HSTROBE edge to latch the data.
4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA
burst is paused, whichever occurs first.
5.5.4.3 Pausing an Ultra DMA data out burst
The following steps shall occur in the order they are listed unless otherwise specifically allowed
(see 5.6.3.9 and 5.6.3.2 for specific timing requirements).
a) Host pausing an Ultra DMA data out burst
1)
The host shall not pause an Ultra DMA burst until at least one data word of an Ultra
DMA burst has been transferred.
2)
The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.
Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst
termination when the host stops generating HSTROBE edges. If the host does not assert
STOP, in order to initiate Ultra DMA burst termination, the device shall negate
DDMARDY- and wait t
3)
The host shall resume an Ultra DMA burst by generating an HSTROBE edge.
after the host has negated STOP. After
LI
for the selected Ultra DMA mode.
CYC
before negating DMARQ.
RP
C141-E110-02EN
after the
LI
after
DVS
after
DVS
after generating an
DVH
5 - 89
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