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Fujitsu C141-E090-02EN Product Manual

Fujitsu computer drive user manual.
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MPE3xxxAH
DISK DRIVES
PRODUCT MANUAL
C141-E090-02EN

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   Summary of Contents for Fujitsu C141-E090-02EN

  • Page 1: Disk Drives

    MPE3xxxAH DISK DRIVES PRODUCT MANUAL C141-E090-02EN...

  • Page 2

    “R” in the explanatory notes of the Table 5.4 is modified. • Section 6.3.1, “Power save mode,” is modified. • REVISION RECORD Revised contents Specification No.: C141-E090-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved. Copyright C141-E090-02EN 1999 FUJITSU LIMITED...

  • Page 3

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  • Page 4

    This manual describes the MPE3xxxAH series, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.

  • Page 5

    Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazarous situation likely to result in serious personal injury if the user does not perform the procedure correctly.

  • Page 6

    "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

  • Page 7

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  • Page 8: Table Of Contents

    CHAPTER 1 DEVICE OVERVIEW ... 1 - 1 Features ... 1 - 1 1.1.1 Functions and performance ... 1 - 1 1.1.2 Adaptability... 1 - 2 1.1.3 Interface... 1 - 2 Device Specifications ... 1 - 4 1.2.1 Specifications summary... 1 - 4 1.2.2 Model and product number ...

  • Page 9

    Jumper Settings ... 3 - 12 3.4.1 Location of setting jumpers ... 3 - 12 3.4.2 Factory default setting ... 3 - 13 3.4.3 Jumper configuration... 3 - 13 CHAPTER 4 THEORY OF DEVICE OPERATION ... 4 - 1 Outline... 4 - 1 Subassemblies ...

  • Page 10

    5.2.1 I/O registers ... 5 - 6 5.2.2 Command block registers ... 5 - 8 5.2.3 Control block registers ... 5 - 13 Host Commands ... 5 - 13 5.3.1 Command code and parameters... 5 - 14 5.3.2 Command descriptions ... 5 - 16 5.3.3 Error posting...

  • Page 11

    5.6.3.5 Device terminating an Ultra DMA data in burst ... 5 - 92 5.6.3.6 Host terminating an Ultra DMA data in burst... 5 - 93 5.6.3.7 Initiating an Ultra DMA data out burst... 5 - 94 5.6.3.8 Sustained Ultra DMA data out burst... 5 - 95 5.6.3.9 Device pausing an Ultra DMA data out burst...

  • Page 12

    Current fluctuation (Typ.) when power is turned on... 1 - 7 Disk drive outerview ... 2 - 1 1 drive system configuration ... 2 - 3 2 drives configuration... 2 - 3 Dimensions... 3 - 2 Orientation... 3 - 3 Limitation of side-mounting...

  • Page 13

    WRITE SECTOR(S) command protocol... 5 - 70 Protocol for the command execution without data transfer ... 5 - 71 Normal DMA data transfer ... 5 - 73 Ultra DMA termination with pull-up or pull-down ... 5 - 84 PIO data transfer timing... 5 - 85 Multiword DMA data transfer timing (mode 2) ...

  • Page 14

    Specifications ... 1 - 4 Model names and product numbers... 1 - 5 Current and power dissipation... 1 - 6 Environmental specifications... 1 - 8 Acoustic noise specification ... 1 - 8 Shock and vibration specification... 1 - 9 Surface temperature measurement points and standard values ... 3 - 5 Cable connector specifications ...

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  • Page 16: Chapter 1 Device Overview

    CHAPTER 1 DEVICE OVERVIEW Overview and features are described in this chapter, and specifications and power requirement are described. The MPE3xxxAH series are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable. Features 1.1.1 Functions and performance...

  • Page 17: Adaptability

    Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 8.5 ms (at read). 1.1.2 Adaptability Power save mode The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor.

  • Page 18

    Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC has improved buffer error correction for correctable data errors. Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media.

  • Page 19: Device Specifications

    Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. MPE3102AH Formatted Capacity (*1) 10.24 GB Number of Disks Number of Heads Number of Cylinders (User + Alternate & SA) Bytes per Sector Recording Method Track Density Bit Density Rotational Speed Average Latency...

  • Page 20: Model And Product Number

    1.2.2 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Capacity Mounting Model Name (user area) MPE3102AH 10.24 GB No. 6-32UNC MPE3136AH 13.66 GB No. 6-32UNC MPE3204AH 20.49 GB No. 6-32UNC MPE3273AH 27.32 GB No.

  • Page 21: Current And Power Dissipation

    Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Typical RMS current (*1) [mA] Mode of Operation +12 V Model 3102AH 3136AH Spin up 1600 1600 1800 peak 1800 peak Idle (Ready) (*3) R/W (On Track) (*4) Seek (Random) (*5)

  • Page 22: Current Fluctuation (typ.) When Power Is Turned On

    Current fluctuation (Typ.) when power is turned on Figure 1.1 Current fluctuation (Typ.) when power is turned on Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

  • Page 23: Environmental Specifications

    Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.4 Temperature • Operating • Non-operating • Thermal Gradient Humidity • Operating • Non-operating • Maximum Wet Bulb Altitude (relative to sea level) • Operating • Non-operating Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Sound Power per ISO 7779 and...

  • Page 24: Shock And Vibration

    Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Vibration (swept sine, one octave per minute) • Operating • Non-operating Shock (half-sine pulse, Operating) • 2 ms duration • 11 ms duration Shock (half-sine pulse, Non-operating) •...

  • Page 25: Error Rate

    Service life In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first.

  • Page 26: Chapter 2 Device Configuration

    CHAPTER 2 DEVICE CONFIGURATION Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.1 Device Configuration System Configuration...

  • Page 27

    Disk The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 40,000 start/stop operations. MPE3102AH: 2 disks MPE3136AH: 2 disks MPE3204AH: 3 disks MPE3273AH: 4 disks...

  • Page 28: System Configuration

    System Configuration 2.2.1 ATA interface Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer till 16.7 MB/s (Multiword DMA mode 2), and the ultra DMA transfer till 66.6 MB/s (Ultra DMA mode 4).

  • Page 29

    IMPORTANT HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-4 interface. At high speed data transfer (PIO mode 3, mode 4, DMA mode 2 or ultra DMA mode 4), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.

  • Page 30: Chapter 3 Installation Conditions

    CHAPTER 3 INSTALLATION CONDITIONS Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Dimensions Mounting Cable Connections Jumper Settings C141-E090-01EN 3 - 1...

  • Page 31: Dimensions

    Figure 3.1 Dimensions 3 - 2 C141-E090-02EN...

  • Page 32: Mounting

    Mounting Orientation Figure 3.2 illustrates normal orientation for the disk drive. The disk drives can be mounted in any orientation. Horizontal mounting with the PCB facing down Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground.

  • Page 33: Limitation Of Side-mounting

    Figure 3.3 Bottom surface mounting Frame of system cabinet 4.5 or less Details of A Figure 3.4 3 - 4 Do not use this screw holes Limitation of side-mounting Side surface mounting Frame of system cabinet Screw 5.0 or less Details of B Mounting frame structure C141-E090-01EN...

  • Page 34: Surface Temperature Measurement Points

    Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.

  • Page 35: Service Area

    Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. - Mounting screw hole [P side] - Cable connection - Mode setting switches External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

  • Page 36: Cable Connections

    Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. Power supply connector (CN1) ATA interface connector (CN1) Power supply connector (CN1) Mode Setting Pins...

  • Page 37: Cable Connector Specifications

    Figure 3.8 shows how to connect the devices. ATA interface cable Host system 3 - 8 Cable connector specifications Name Model FCN-707B040-AU/B FCN-707B040-AU/O 1-480424-0 60617-4 Power supply cable Disk Drive #0 Disk Drive #1 Figure 3.8 Cable connections C141-E090-01EN Manufacturer Fujitsu Fujitsu power supply...

  • Page 38: System Configuration For Ultra Dma

    3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). (Viewed from cable side) Figure 3.9 3.3.5 System configuration for Ultra DMA Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O ports.

  • Page 39: Cable Configuration

    127.0 to 304.8 mm (5 to 12 inch) Pin 40 (Ground) open Pin 34 Pin 30 (Ground) Symbolizes Pin 34 Pin 26 (Ground) Conductor being cut Pin 24 (Ground) Pin 22 (Ground) Pin 19 (Ground) Pin 2 (Ground) System Board Connector Figure 3.10 Cable configuration b) Host system that do not support Ultra DMA modes greater than mode 2 shall not connect...

  • Page 40: Cable Type Detection Using Cblid- Signal (host Sensing The Condition Of The Cblid- Signal)

    Host detected CBLID- above V PDIAG-: CBLID- conductor Host Device 1 Device 0 with 40-conductor cable Figure 3.11 Cable type detection using CBLID- signal (Host sensing the condition of the CBLID- signal) IDENTIFY DEVICE information word 93 bit13:0 Device detected CBLID- below V PDIAG-:CBLID- conductor 0.047 F ±10% or...

  • Page 41: Jumper Settings

    Jumper Settings 3.4.1 Location of setting jumpers Figure 3.13 shows the location of the jumpers to select drive configuration and functions. DC Power Connector 3 - 12 Interface Connector Figure 3.13 Jumper location C141-E090-01EN...

  • Page 42: Factory Default Setting

    3.4.2 Factory default setting Figure 3.14 shows the default setting position at the factory. (Master device setting) DC Power Connector Figure 3.14 Factory default setting 3.4.3 Jumper configuration Device type Master device (device #0) or slave device (device #1) is selected. (a) Master device Figure 3.15 Jumper setting of master or slave device Note:...

  • Page 43: Jumper Setting Of Cable Select

    CSEL connected to the interface cable selection can be done by the special interface cable. Figure 3.16 Jumper setting of Cable Select Figures 3.17 and 3.18 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level.

  • Page 44

    Special jumper settings (a) 2.1 GB clip (Limit capacity to 2.1 GB) If the drive cannot be recognized by system with legacy BIOS’s which do not allow single volume sizes greater than approximately 2.1 GB, the following jumper settings should be applied.

  • Page 45

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  • Page 46: Chapter 4 Theory Of Device Operation

    CHAPTER 4 THEORY OF DEVICE OPERATION This chapter explains basic design concepts of the disk drive. subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks. Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive.

  • Page 47: Head

    4.2.2 Head Figure 4.1 shows the read/write head structures. The Numerals 0 to 7 indicate read/write heads. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed. MPE3102AH Spindle MPE3204AH Spindle 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor.

  • Page 48: Air Filter

    4.2.5 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.

  • Page 49: Circuit Configuration

    Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

  • Page 50: Mpe3xxxah Block Diagram

    Figure 4.2 MPE3xxxAH Block diagram C141-E090-01EN 4 - 5...

  • Page 51: Power-on Sequence

    Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. successfully, the disk drive starts the spindle motor.

  • Page 52: Power-on Operation Sequence

    Power on Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. Self-diagnosis 2 • Data buffer write/read test Confirming spindle motor speed Release heads from actuator lock Initial on-track and read out of system information Execute self-calibration Drive ready state...

  • Page 53: Self-calibration

    Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.

  • Page 54: Execution Timing Of Self-calibration

    4.5.2 Execution timing of self-calibration Self-calibration is executed when: The power is turned on. The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. The timechart is shown in Table 4.1. After power-on, self-calibration is performed about every 30 minutes.

  • Page 55: Read/write Circuit

    Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the synthesizer in the read channel (RDC). 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mounted on the FPC. The PreAMP consists of an 4 or 8-channel read preamplifier and a write current switch and senses a write error.

  • Page 56: Read Circuit

    4.6.3 Read circuit The head read signal from the PreAMP is regulated by the variable gain amplifier (VGA) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 48/51 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 57: Synthesizer Circuit

    4.6.4 Synthesizer circuit The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant.

  • Page 58: Servo Control Circuit

    4.7.1 Servo control circuit Figure 4.4 is the block diagram of the servo control circuit. The following describes the functions of the blocks: Servo Head burst capture Position Sense CSR: Current Sense Resistor VCM: Voice Coil Motor Figure 4.4 Microprocessor unit (MPU) The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to the reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operations of the MPU.

  • Page 59: Physical Sector Servo Configuration On Disk Surface

    c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value. Figure 4.5 Physical sector servo configuration on disk surface 4 - 14 Servo frame...

  • Page 60

    Servo burst capture circuit The four servo signals can be synchronously detected by the STROB signal, full-wave rectified integrated. A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.

  • Page 61: Data-surface Servo Format

    4.7.2 Data-surface servo format Figure 4.5 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.6 are described below. Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

  • Page 62: 72 Servo Frames In Each Track

    0.24 s 1.64 s 1.16 s W/R Recovery Field 7.98 s Servo DATA Frame Figure 4.6 Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. Servo mark (SMK1, SMK2) This area generates a timing for demodulating the gray code and position-demodulating Pos A to D by detecting the servo mark.

  • Page 63: Actuator Motor Control

    Preamble This area is used to synchronize with the PLL, which is used to search the SSM by detecting the ASM. Gray code (including index bit) This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit.

  • Page 64: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control;...

  • Page 65

    e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC.

  • Page 66: Chapter 5 Interface

    CHAPTER 5 INTERFACE Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA feature set Timing C141-E090-01EN 5 - 1...

  • Page 67: Physical Interface

    Physical Interface 5.1.1 Interface signals Table 5.1 shows the interface signals. Description Cable select Chip select 0 Chip select 1 Data bus bit 0 Data bus bit 1 Data bus bit 2 Data bus bit 3 Data bus bit 4 Data bus bit 5 Data bus bit 6 Data bus bit 7...

  • Page 68: Signal Assignment On The Connector

    5.1.2 Signal assignment on the connector Table 5.2 shows the signal assignment on the interface connector. Table 5.2 Signal assignment on the interface connector Pin No. RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DMARQ DIOW–, STOP DIOR–, HDMARDY–, HSTROBE IORDY, DDMARDY–, DSTROBE DMACK–...

  • Page 69

    [signal] [I/O] DIOR– HDMARDY– HSTROBE INTRQ CS0– CS1– DA 0-2 – PIDAG– CBLID– DASP– 5 - 4 [Description] DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts.

  • Page 70

    [signal] [I/O] IORDY This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts.

  • Page 71: Logical Interface

    Logical Interface The device can operate for command execution in either address-specified mode; cylinder- head-sector (CHS) or Logical block address (LBA) mode. information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.

  • Page 72: I/o Registers

    CS0– CS1– Command block registers Control block registers Notes: The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15). The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

  • Page 73: Command Block Registers

    5.2.2 Command block registers Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

  • Page 74: Diagnostic Code

    [Diagnostic code] X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.

  • Page 75

    Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. Cylinder High register (X'1F5') The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

  • Page 76

    Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.

  • Page 77

    - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit.

  • Page 78: Control Block Registers

    5.2.3 Control block registers Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

  • Page 79: Command Code And Parameters

    5.3.1 Command code and parameters Table 5.4 lists the supported commands, command code and the registers that needed parameters are written. Table 5.4 Command name READ SECTOR(S) READ MULTIPLE READ DMA READ VERIFY SECTOR(S) WRITE MULTIPLE WRITE DMA WRITE VERIFY WRITE SECTOR(S) RECALIBRATE SEEK...

  • Page 80

    D*: The command is addressed to the master device, but both the master device and the slave device execute it. X: Do not care Command code and parameters (2 of 2) Command code (Bit) CY: Cylinder Registers DH : Drive/Head Register C141-E090-02EN Parameters used FR SC SN CY DH 5 - 15...

  • Page 81: Command Descriptions

    5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) (CM) (DH) (CH)

  • Page 82

    Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). At error occurrence, the SC register indicates the remaining sector count of data transfer.

  • Page 83

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ MULTIPLE (X'C4') This command operates similarly to the READ SECTOR(S) command.

  • Page 84: Execution Example Of Read Multiple Command

    Figure 5.1 shows an example of the execution of the READ MULTIPLE command. Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) Number of sectors in incomplete block = remainder of 9/4 =1 Command Issue Parameter...

  • Page 85

    READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer.

  • Page 86

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ VERIFY SECTOR(S) (X'40' or X'41') This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.

  • Page 87

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE SECTOR(S) (X'30' or X'31') This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count...

  • Page 88

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE MULTIPLE (X'C5') This command is similar to the WRITE SECTOR(S) command.

  • Page 89

    The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) (CM) (DH) (CH)

  • Page 90

    1) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 2) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents) (CM) (DH)

  • Page 91

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. RECALIBRATE (X'1x', x: X'0' to X'F') This command performs the calibration.

  • Page 92

    (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.

  • Page 93

    (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters.

  • Page 94

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E090-01EN 5 - 29...

  • Page 95: Information To Be Read By Identify Device Command

    Table 5.5 Information to be read by IDENTIFY DEVICE command (1 of 4) Word Value X‘045A’ General Configuration *1 Number of cylinders X‘0000’ Reserved Number of Heads X‘0000’ Retired X‘0000’ Retired X‘003F’ Number of sectors per track X‘000000000000’ Retired 10-19 –...

  • Page 96

    Table 5.5 Information to be read by IDENTIFY DEVICE command (2 of 4) *1 Word 0: General configuration Bit 15: 0 = ATA device Bit 14-8: Vendor specific Bit 7: 1 = Removable media device Bit 6: 1 = not removable controller and/or device Bit 5-1: Vendor specific Bit 0: Reserved *2 Number of Cylinders, *3 Number of Heads,...

  • Page 97

    Table 5.5 Information to be read by IDENTIFY DEVICE command (3 of 4) *12 Word 63: Multiword DMA transfer mode Bit 15-8: Currently used multiword DMA transfer mode Bit 7-0: Supportable multiword DMA transfer mode Bit 2=1 Mode 2 Bit 1=1 Mode 1 Bit 0=1 Mode 0 *13 Word 64: Advance PIO transfer mode support status Bit 15-8: Reserved...

  • Page 98

    Table 5.5 Information to be read by IDENTIFY DEVICE command (4 of 4) *17 Word 85: Enable/disable Command set/feature enabled Bit 15: Reserved Bit 14: NOP command supported = 0 Bit 13: READ BUFFER command supported = 0 Bit 12: WRITE BUFFER command supported = 0 Bit 11: Reserved...

  • Page 99

    (13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL)

  • Page 100: Features Register Values And Settable Modes

    Table 5.6 Features Register X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘04’ No operation. X‘05’ Enable the advanced power management function. X‘33’...

  • Page 101

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected.

  • Page 102

    (15) SET MULTIPLE MODE (X'C6') This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command. The number of sectors per block is written into the Sector Count register.

  • Page 103

    Regarding software reset, the mode set prior to software reset is retained after software reset. The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below. See Subsection 5.3.2 for the IDENTIFY DEVICE command.

  • Page 104

    Code X‘01’ X‘03’ X‘05’ X‘8x’ At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (17) FORMAT TRACK (X'50') Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512- byte format parameter transfer from the host system.

  • Page 105

    The READ LONG command supports only single sector operation. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 or 1 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC)

  • Page 106

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 or 1 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, this register indicates 01. (20) READ BUFFER (X'E4') The host system can read the current contents of the sector buffer of the device by issuing this...

  • Page 107

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register.

  • Page 108

    (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.

  • Page 109

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.

  • Page 110

    (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.

  • Page 111

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (26) SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode.

  • Page 112

    At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers.

  • Page 113

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (28) SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.

  • Page 114: Features Register Values (subcommands) And Functions

    Table 5.8 Features Register values (subcommands) and functions Features Resister X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512- byte attribute value information to the host.

  • Page 115

    Alternative, the device must issue the SMART Enable-Disable Attribute AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium. The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers.

  • Page 116: Format Of Device Attribute Value Data

    The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below.

  • Page 117: Format Of Insurance Failure Threshold Value Data

    Table 5.10 Format of insurance failure threshold value data Byte Attribute 1 Threshold 1 (Threshold of attribute 1) Threshold 2 to threshold 30 Reserved Unique to vendor Check sum Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds.

  • Page 118

    Attribute ID The attribute ID is defined as follows: Attribute ID (Indicates unused attribute data.) Read error rate Throughput performance Spin up time Number of times the spindle motor is activated Number of alternative sectors Seek error rate Seek time performance Power-on time Number of retries made to activate the spindle motor Number of power-on-power-off times...

  • Page 119

    Raw attribute value Raw attributes data is retained. Failure prediction capability flag Bit 0: The attribute value data is saved to a medium before the device enters power saving mode. Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation.

  • Page 120

    (29) FLUSH CACHE (X ‘E7’) This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs.

  • Page 121: Contents Of Security Password

    (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

  • Page 122

    At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command.

  • Page 123

    At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (32) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.

  • Page 124

    At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (33) SECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.

  • Page 125

    READ DMA READ LONG READ MULTIPLE READ SECTORS At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set.

  • Page 126: Contents Of Security Set Password Data

    Table 5.12 Contents of SECURITY SET PASSWORD data Word Control word Bit 0 Identifier 0 = Sets a user password. 1 = Sets a master password. Bits 1 to 7 Reserved Bit 8 Security level 0 = High 1 = Maximum Bits 9 to 15 Reserved 1 to 16 Password (32 bytes)

  • Page 127

    At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (35) SECURITY UNLOCK (F2h) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 1.1 to the device. Operation of the device varies as follows depending on whether the host specifies the master password or user password.

  • Page 128

    At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (36) SET MAX ADDRESS (F9) This command allows the maximum address accessible by the user to be set in LBA or CHS mode.

  • Page 129

    At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (37) READ NATIVE MAX ADDRESS (F8) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command.

  • Page 130

    At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information C141-E090-01EN Max head/LBA [MSB] 5 - 65...

  • Page 131: Command Code And Parameters

    5.3.3 Error posting Table 5.14 lists the defined errors that are valid for each command. Table 5.14 Command code and parameters Command name READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE READ DMA WRITE DMA WRITE VERIFY READ VERIFY SECTOR(S) RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS...

  • Page 132: Command Protocol

    Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

  • Page 133: Read Sector(s) Command Protocol

    Command Parameter write DRDY INTRQ Data transfer Expanded Command Min. 30 s (*1) INTRQ Data Reg. Selection Data IOR- Word IOCS16- *1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. Figure 5.2 Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer.

  • Page 134: Data Transferring Commands From Host To Device

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.

  • Page 135: Write Sector(s) Command Protocol

    a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit.

  • Page 136: Commands Without Data Transfer

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.

  • Page 137: Other Commands

    5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

  • Page 138: Normal Dma Data Transfer

    Command Parameter write c, d DRDY INTRQ Data transfer Expanded [Multiword DMA transfer] DMARQ DMACK- IOR- or IOW- Word Figure 5.6 • • • • • • • • • • • • • • • • • • • • • • Normal DMA data transfer C141-E090-01EN Status read...

  • Page 139: Ultra Dma Feature Set

    Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.

  • Page 140: Phases Of Operation

    5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).

  • Page 141: The Data In Transfer

    11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within t host has negated STOP and asserted HDMARDY-.

  • Page 142: Terminating An Ultra Dma Data In Burst

    The device shall stop generating DSTROBE edges within t HDMARDY-. If the host negates HDMARDY- within t DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.

  • Page 143

    10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

  • Page 144: Ultra Dma Data Out Commands

    10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than t calculation on DD (15:0).

  • Page 145: The Data Out Transfer

    9) The device shall assert DDMARDY- within t asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

  • Page 146: Terminating An Ultra Dma Data Out Burst

    b) Device pausing an Ultra DMA data out burst The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. The device shall pause an Ultra DMA burst by negating DDMARDY-. The host shall stop generating HSTROBE edges within t DDMARDY-.

  • Page 147

    The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

  • Page 148: Ultra Dma Crc Rules

    11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

  • Page 149: Series Termination Required For Ultra Dma

    I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

  • Page 150: Pio Data Transfer Timing

    Timing 5.6.1 PIO data transfer Figure 5.8 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Cycle time Data register selection setup time for DIOR-/DIOW- Pulse width of DIOR-/DIOW- Recovery time of DIOR-/DIOW- Data setup time for DIOW-...

  • Page 151: Multiword Data Transfer

    5.6.2 Multiword data transfer Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Cycle time Delay time from DMACK assertion to DMARQ negation Pulse width of DIOR-/DIOW- Data setup time for DIOR- Data hold time for DIOR-...

  • Page 152: Ultra Dma Data Transfer

    5.6.3 Ultra DMA data transfer Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts. Table 5.16 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

  • Page 153: Ultra Dma Data Burst Timing Requirements

    5.6.3.2 Ultra DMA data burst timing requirements Table 5.16 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 (in ns) (in ns) 2CYCTYP 2CYC IORDYZ 5 - 88 MODE 2 MODE 3 MODE 4 (in ns) (in ns) (in ns) MAX (see Notes 1 and 2)

  • Page 154

    Table 5.16 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 (in ns) (in ns) ZIORDY Notes: 1) Unless otherwise specified, timing parameters shall be measured at the connector of the se nder or receiver to which the parameter applies (see Note 5 for exceptions).

  • Page 155: Sustained Ultra Dma Data In Burst

    5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

  • Page 156: Host Pausing An Ultra Dma Data In Burst

    5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.

  • Page 157: Device Terminating An Ultra Dma Data In Burst

    5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.13 Device terminating an Ultra DMA data in burst 5 - 92 C141-E090-01EN...

  • Page 158: Host Terminating An Ultra Dma Data In Burst

    5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.14 Host terminating an Ultra DMA data in burst C141-E090-01EN 5 - 93...

  • Page 159: Initiating An Ultra Dma Data Out Burst

    5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.15 Initiating an Ultra DMA data out burst 5 - 94 C141-E090-01EN...

  • Page 160: Sustained Ultra Dma Data Out Burst

    5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

  • Page 161: Device Pausing An Ultra Dma Data Out Burst

    5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.

  • Page 162: Host Terminating An Ultra Dma Data Out Burst

    5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.18 Host terminating an Ultra DMA data out burst C141-E090-01EN 5 - 97...

  • Page 163: Device Terminating An Ultra Dma Data Out Burst

    5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.19 Device terminating an Ultra DMA data out burst 5 - 98 C141-E090-01EN...

  • Page 164: Power-on And Reset

    5.6.4 Power-on and reset Figure 5.20 shows power-on and reset (hardware and software reset) timing. Only master device is present Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. Master and slave devices are present (2-drives configuration) [Master device] DASP- [Slave device]...

  • Page 165

    This page is intentionally left blank.

  • Page 166: Chapter 6 Operations

    CHAPTER 6 OPERATIONS Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. Device Response to the Reset Address Translation Power Save Defect Management...

  • Page 167: Response To Power-on

    6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 168: Response To Hardware Reset

    6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 169: Response To Software Reset

    6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 170: Response To Diagnostic Command

    6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.

  • Page 171: Address Translation

    Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.2.1 Default parameters In the logical to physical address translation, the logical cylinder, head, and sector addresses...

  • Page 172: Logical Address

    6.2.2 Logical address CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent sector from the last sector of the current physical head address.

  • Page 173: Power Save

    ..... . 1006 ..... . Address translation (example in LBA mode) C141-E090-02EN 1007...

  • Page 174

    A reset is issued in the sleep mode. When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode. Reset (hardware or software) STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command C141-E090-02EN 6 - 9...

  • Page 175: Power Commands

    INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.

  • Page 176: Spare Area

    6.4.1 Spare area Following two types of spare area are provided in the user space. 1) Spare sector for sector slip: used for alternating defective sectors at formatting in shipment in case that a physical track contains one or two defective sectors (2 sectors/track) 2) Spare cylinder for alternative assignment: used for alternative assignment for the third and subsequent defective sectors in case that a physical track contains three or more defective sectors, and also used by automatic...

  • Page 177: Alternate Cylinder Assignment

    Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when a physical track contains three or more defective sectors, and when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0. Index Sector (physical) Cylinder 0...

  • Page 178: Read-ahead Cache

    Read-Ahead Cache After a read command which reads the data from the disk medium is completed, the read- ahead cache function reads the subsequent data blocks automatically and stores the data in the data buffer. When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium.

  • Page 179: Caching Operation

    6.5.2 Caching operation The caching operation is performed only at receipt of the following commands. The device transfers data from the data buffer to the host system if the following data exist in the data buffer. All sector data to be processed by the command A part of data including the starting sector to be processed by the command When a part of data to be processed exist in the data buffer, the remaining data are read from the disk medium and are transferred to the host system.

  • Page 180: Usage Of Read Segment

    6.5.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases. Miss-hit (no hit) A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media. 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the sequential address to the last read segment.

  • Page 181

    Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive tries to fill the buffer space with the read ahead data. a. Sequential command just after non-sequential command At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data.

  • Page 182

    b. Sequential hit When the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system. The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.

  • Page 183

    Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation.

  • Page 184

    1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. Partially hit data 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.

  • Page 185: Write Cache

    Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.

  • Page 186

    At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state.

  • Page 187

    8F, Hun Tai Center, 168-170, Tun Hwa North Road, 1st Sec., Taipei, TAIWAN TEL: 886-2-545-7700 FAX: 886-2-717-4644 FUJITSU SYSTEMS BUSINESS (MALAYSIA) SDN. BHD. Fujitsu Plaza, 1A, Jalan Tandang 204, P.O. Box 636 Pejabat Pos Jalan Sultan 46770 Petaling Jaya, Selangor Darul Ehsan, Malaysia TEL: 60-3-793-3888 FAX: 60-3-793-0888 FUJITSU SYSTEMS BUSINESS (THAILAND) LTD.

  • Page 188

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