Fujitsu MPF3XXXAH Product Manual
  1. Manuals
  2. Brands
  3. Fujitsu Manuals
  4. Storage
  5. MPF3XXXAH
  6. Product manual
Fujitsu MPF3XXXAH Product Manual

Fujitsu MPF3XXXAH Product Manual

Fujitsu computer drive user manual
Hide thumbs Also See for MPF3XXXAH:
Table of Contents

Advertisement

Quick Links

Download this manual
C141-E106-02EN

Advertisement

Table of Contents
loading

Related Manuals for Fujitsu MPF3XXXAH

Summary of Contents for Fujitsu MPF3XXXAH

  • Page 1 C141-E106-02EN...
  • Page 2 ¤...
  • Page 7 LQMXU\ SHUVRQDOLQMXU\ +$ KRVW DGDSWHU  FRQVLVWV RI DGGUHVV GHFRGHU GULYHU DQG UHFHLYHU $7$ LV DQ DEEUHYLDWLRQ RI $7 DWWDFKPHQW  7KH GLVN GULYH LV FRQIRUPHGWRWKH$7$LQWHUIDFH OLNHO\ VHULRXVSHUVRQDO FRXOG SHUVRQDOLQMXU\ FRXOG PLQRU PRGHUDWH...

  • Page 28: Device Configuration

    CHAPTER 2 DEVICE CONFIGURATION Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.1 Device Configuration System Configuration...
  • Page 29 Disk The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 40,000 start/stop operations. MPF3102AH: 1 disks MPF3153AH: 2 disks MPF3204AH: 2 disks Head...
  • Page 30 System Configuration 2.2.1 ATA interface Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer till 16.7 MB/s (Multiword DMA mode 2), and the ultra DMA transfer till 66.6 MB/s (Ultra DMA mode 4).
  • Page 32 CHAPTER 3 INSTALLATION CONDITIONS Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Dimensions Handling Cautions Mounting Cable Connections Jumper Settings C141-E106-01EN 3 - 1...
  • Page 33 Figure 3.1 Dimensions 3 - 2 C141-E106-01EN...
  • Page 34 +DQGOLQJ&DXWLRQV  *HQHUDOQRWHV :ULVWVWUDS  ,QVWDOODWLRQ  5HFRPPHQGHGHTXLSPHQWV 6KRFNDEVRUELQJPDW )LJXUH +DQGOLQJFDXWLRQV (6'PDW...
  • Page 35 Mounting Direction Figure 3.3 illustrates normal direction for the disk drive. The disk drives can be mounted in any direction. Horizontal mounting with the PCB facing down Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground.
  • Page 36 Figure 3.4 Bottom surface mounting Frame of system cabinet 4.5 or less Details of A Figure 3.5 Do not use this screw holes Limitation of side-mounting Side surface mounting Frame of system cabinet Screw 5.0 or less Details of B Mounting frame structure C141-E106-01EN Use these screw...
  • Page 37 Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.
  • Page 38 Service area Figure 3.7 shows how the drive must be accessed (service areas) during and after installation. - Mounting screw hole [P side] - Cable connection - Mode setting switches External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.
  • Page 39 &DEOH&RQQHFWLRQV  'HYLFHFRQQHFWRU )LJXUH &RQQHFWRUORFDWLRQV...
  • Page 41 3.4.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). (Viewed from cable side) Figure 3.10 Power supply connector pins (CN1) 3.4.5 System configuration for Ultra DMA Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O ports.
  • Page 42 127.0 to 304.8 mm (5 to 12 inch) Pin 40 (Ground) open Pin 34 Pin 30 (Ground) Symbolizes Pin 34 Pin 26 (Ground) Conductor being cut Pin 24 (Ground) Pin 22 (Ground) Pin 19 (Ground) Pin 2 (Ground) System Board Connector Figure 3.11 Cable configuration b) Host system that do not support Ultra DMA modes greater than mode 2 shall not connect to...
  • Page 43 Host detected CBLID- above V PDIAG-: CBLID- conductor Host Device 1 with 40-conductor cable Figure 3.12 Cable type detection using CBLID- signal IDENTIFY DEVICE information word 93 bit13:0 Device detected CBLID- below V PDIAG-:CBLID- conductor 0.047 F ±10% or ±20% Host Device 1 with 40-conductor cable...
  • Page 44 -XPSHU6HWWLQJV  /RFDWLRQRIVHWWLQJMXPSHUV )LJXUH -XPSHUORFDWLRQ...
  • Page 45 3.5.2 Factory default setting Figure 3.15 shows the default setting position at the factory. (Master device setting) DC Power Connector Figure 3.15 Factory default setting 3.5.3 Jumper configuration Device type Master device (device #0) or slave device (device #1) is selected. (a) Master device Figure 3.16 Jumper setting of master or slave device Note:...
  • Page 46 CSEL connected to the interface cable selection can be done by the special interface cable. Figure 3.17 Jumper setting of Cable Select Figures 3.18 and 3.19 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level.
  • Page 47 Special jumper settings (a) 2.1 GB clip (Limit capacity to 2.1 GB) If the drive cannot be recognized by system with legacy BIOS’s which do not allow single volume sizes greater than approximately 2.1 GB, the following jumper settings should be applied.

  • Page 48: Chapter 4 Theory Of Device Operation

    CHAPTER 4 THEORY OF DEVICE OPERATION This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks. Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive.
  • Page 49  +HDG  6SLQGOH  $FWXDWRU )LJXUH +HDGVWUXFWXUH...
  • Page 50 4.2.5 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.
  • Page 51 &LUFXLW&RQILJXUDWLRQ...
  • Page 53 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. successfully, the disk drive starts the spindle motor.
  • Page 54 Power on Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. Self-diagnosis 2 • Data buffer write/read test Confirming spindle motor speed Release heads from actuator lock Initial on-track and read out of system information Execute self-calibration Drive ready state...
  • Page 55 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.
  • Page 56 4.5.2 Execution timing of self-calibration Self-calibration is executed when: The power is turned on. The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. The timechart is shown in Table 4.1. performed about every 30 minutes.
  • Page 58  5HDGFLUFXLW...
  • Page 59  6\QWKHVL]HUFLUFXLW 7DEOH 6HUYR&RQWURO 7UDQVIHUUDWHRIHDFK]RQH...
  • Page 60 4.7.1 Servo control circuit Figure 4.4 is the block diagram of the servo control circuit. functions of the blocks: Servo Head burst capture Position Sense CSR: Current Sense Resistor VCM: Voice Coil Motor Figure 4.4 Microprocessor unit (MPU) The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to the reference cylinders, seeks the specified cylinder, and executes calibration according to the internal operations of the MPU.
  • Page 61 c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value. Figure 4.5 Physical sector servo configuration on disk surface 4 - 14 Servo frame...
  • Page 62 Servo burst capture circuit The four servo signals can be synchronously detected by the DEMOD signal (internal), full-wave rectified integrated. A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.
  • Page 63 4.7.2 Data-surface servo format Figure 4.5 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.6 are described below. Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.
  • Page 64 )LJXUH VHUYRIUDPHVLQHDFKWUDFN...
  • Page 65 Preamble This area is used to synchronize with the PLL, which is used to search the SSM by detecting the ASM. Gray code (including index bit) This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit.
  • Page 66 (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control;...
  • Page 67 Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 7,200 rpm.

  • Page 69: Physical Interface

    Physical Interface 5.1.1 Interface signals Table 5.1 shows the interface signals. Description Cable select Chip select 0 Chip select 1 Data bus bit 0 Data bus bit 1 Data bus bit 2 Data bus bit 3 Data bus bit 4 Data bus bit 5 Data bus bit 6 Data bus bit 7...
  • Page 70 5.1.2 Signal assignment on the connector Table 5.2 shows the signal assignment on the interface connector. Table 5.2 Pin No. RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DMARQ DIOW–, STOP DIOR–, HDMARDY–, HSTROBE IORDY, DDMARDY–, DSTROBE DMACK– INTRQ CS0–...
  • Page 71 [signal] [I/O] DIOR– HDMARDY– HSTROBE INTRQ CS0– CS1– DA 0-2 – PIDAG– CBLID– DASP– 5 - 4 [Description] DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.
  • Page 72 [signal] [I/O] IORDY This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts.
  • Page 73 Logical Interface The device can operate for command execution in either address-specified mode; cylinder-head- sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.
  • Page 74 CS0– CS1– Command block registers Control block registers Notes: The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15). The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).
  • Page 75 5.2.2 Command block registers Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
  • Page 76 [Diagnostic code] X'01': No Error Detected. X'02': HDC Register Compare Error X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
  • Page 77 Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. Cylinder High register (X'1F5') The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.
  • Page 78 Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
  • Page 79 - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit.
  • Page 80 5.2.3 Control block registers Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
  • Page 81 5.3.1 Command code and parameters Table 5.4 lists the supported commands, command code and the registers that needed parameters are written. Table 5.4 Command name READ SECTOR(S) READ MULTIPLE READ DMA READ VERIFY SECTOR(S) WRITE MULTIPLE WRITE DMA WRITE VERIFY WRITE SECTOR(S) RECALIBRATE SEEK...
  • Page 82 Table 5.4 Command name STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART FLUSH CACHE SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK SET MAX ADDRESS READ NATIVE MAX ADDRESS Notes: FR : Features Register SC : Sector Count Register SN : Sector Number Register R: R = 0 or 1...
  • Page 83 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 84 Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). At error occurrence, the SC register indicates the remaining sector count of data transfer.
  • Page 85 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ MULTIPLE (X'C4') This command operates similarly to the READ SECTOR(S) command.
  • Page 86 Figure 5.1 shows an example of the execution of the READ MULTIPLE command. Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) Number of sectors in incomplete block = remainder of 9/4 =1 Command Issue Parameter...
  • Page 87 READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer.
  • Page 88 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. READ VERIFY SECTOR(S) (X'40' or X'41') This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.
  • Page 89 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE SECTOR(S) (X'30' or X'31') This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count...
  • Page 90 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. WRITE MULTIPLE (X'C5') This command is similar to the WRITE SECTOR(S) command.
  • Page 91 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 92 1) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command 2) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command At command issuance (I/O registers setting contents) (CM) (DH)
  • Page 93 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. RECALIBRATE (X'1x', x: X'0' to X'F') This command performs the calibration.
  • Page 94 (10) SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.
  • Page 95 (11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.
  • Page 101 (13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL)
  • Page 102 7DEOH )HDWXUHVUHJLVWHUYDOXHVDQGVHWWDEOHPRGHV...
  • Page 103 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected.
  • Page 104 (15) SET MULTIPLE MODE (X'C6') This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command. The number of sectors per block is written into the Sector Count register.
  • Page 105 Regarding software reset, the mode set prior to software reset is retained after software reset. The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below. IDENTIFY DEVICE command. Word 47 = 8010: Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 16 (fixed).
  • Page 106 Code X‘01’ X‘03’ X‘05’ X‘8x’ At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (17) FORMAT TRACK (X'50') Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-byte format parameter transfer from the host system.
  • Page 107 The READ LONG command supports only single sector operation. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 or 1 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC)
  • Page 108 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) R = 0 or 1 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) *1 If the command is terminated due to an error, this register indicates 01. (20) READ BUFFER (X'E4') The host system can read the current contents of the sector buffer of the device by issuing this...
  • Page 109 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register.
  • Page 110 (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.
  • Page 111 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 112 (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
  • Page 113 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (26) SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode.
  • Page 114 At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers.
  • Page 115 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (28) SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.
  • Page 116 7DEOH)HDWXUHV5HJLVWHUYDOXHV VXEFRPPDQGV DQGIXQFWLRQV...
  • Page 117 The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers. If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life .
  • Page 118 The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below.
  • Page 119 Table 5.10 Format of insurance failure threshold value data Byte Attribute 1 Threshold 1 (Threshold of attribute 1) Threshold 2 to threshold 30 Reserved Unique to vendor Check sum Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds.
  • Page 120 Attribute ID The attribute ID is defined as follows: Attribute ID (Indicates unused attribute data.) Read error rate Throughput performance Spin up time Number of times the spindle motor is activated Number of alternative sectors Seek error rate Seek time performance Power-on time Number of retries made to activate the spindle motor Number of power-on-power-off times...
  • Page 121 Raw attribute value Raw attributes data is retained. Failure prediction capability flag Bit 0: The attribute value data is saved to a medium before the device enters power saving mode. Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation.
  • Page 123 (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.
  • Page 124 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command.
  • Page 125 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (32) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.
  • Page 128 Table 5.12 Contents of SECURITY SET PASSWORD data Word Control word Bit 0 Identifier 0 = Sets a user password. 1 = Sets a master password. Bits 1 to 7 Reserved Bit 8 Security level 0 = High 1 = Maximum Bits 9 to 15 Reserved 1 to 16 Password (32 bytes)
  • Page 129 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (35) SECURITY UNLOCK (F2h) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 1.1 to the device. Operation of the device varies as follows depending on whether the host specifies the master password or user password.
  • Page 130 At command issuance (I-O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (36) SET MAX ADDRESS (F9) This command allows the maximum address accessible by the user to be set in LBA or CHS mode.
  • Page 131 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (37) READ NATIVE MAX ADDRESS (F8) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command.
  • Page 132 At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information C141-E106-01EN Max head/LBA [MSB] 5 - 65...

  • Page 133: Table Of Contents

    5.3.3 Error posting Table 5.14 lists the defined errors that are valid for each command. Table 5.14 Command code and parameters Command name READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE READ DMA WRITE DMA WRITE VERIFY READ VERIFY SECTOR(S) RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS...

  • Page 134: Read Sector(S)

    Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to Commands can be executed only when the DRDY bit of the Status register is 1.
  • Page 135 Command Parameter write DRDY INTRQ Data transfer Expanded Command Min. 30 s (*1) INTRQ Data Reg. Selection Data IOR- Word IOCS16- *1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. Figure 5.2 Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer.

  • Page 136: Write Sector(S)

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.
  • Page 137 )LJXUH :5,7(6(&725 6 FRPPDQGSURWRFRO...

  • Page 138: Recalibratev

    Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 5 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
  • Page 139 5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.
  • Page 140 Command Parameter write c, d DRDY INTRQ Data transfer Expanded [Multiword DMA transfer] DMARQ DMACK- IOR- or IOW- Word Figure 5.6 • • • • • • • • • • • • • • • • • • • • • • Normal DMA data transfer C141-E106-01EN Status read...
  • Page 141 Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).
  • Page 142 5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).
  • Page 143 11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within t has negated STOP and asserted HDMARDY-.
  • Page 144 The device shall stop generating DSTROBE edges within t HDMARDY-. If the host negates HDMARDY- within t edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t edge, then the host shall be prepared to receive zero, one or two additional data words.
  • Page 145 10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).
  • Page 146 10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than t DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than t calculation on DD (15:0).
  • Page 147 9) The device shall assert DDMARDY- within t asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.
  • Page 148 b) Device pausing an Ultra DMA data out burst The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. The device shall pause an Ultra DMA burst by negating DDMARDY-. The host shall stop generating HSTROBE edges within t DDMARDY-.
  • Page 149 The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).
  • Page 150 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).
  • Page 152 Timing 5.6.1 PIO data transfer Figure 5.8 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Cycle time Data register selection setup time for DIOR-/DIOW- Pulse width of DIOR-/DIOW- Recovery time of DIOR-/DIOW- Data setup time for DIOW-...
  • Page 153 5.6.2 Multiword data transfer Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Cycle time Delay time from DMACK assertion to DMARQ negation Pulse width of DIOR-/DIOW- Data setup time for DIOR- Data hold time for DIOR-...

  • Page 155: Ultra Dma Data Burst Timing Requirements

    5.6.3.2 Ultra DMA data burst timing requirements Table 5.16 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 (in ns) (in ns) 2CYCTYP 2CYC IORDYZ 5 - 88 MODE 2 MODE 3 MODE 4 (in ns) (in ns) (in ns) MAX (see Notes 1 and 2)
  • Page 156 Table 5.16 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 (in ns) (in ns) ZIORDY Notes: 1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies (see Note 5 for exceptions).
  • Page 157 '6752%( DWGHYLFH ''  DWGHYLFH '6752%( DWKRVW ''  DWKRVW...
  • Page 162 +6752%( DWKRVW ''  DWKRVW +6752%( DWGHYLFH ''  DWGHYLFH...
  • Page 166 5.6.4 Power-on and reset Figure 5.20 shows power-on and reset (hardware and software reset) timing. Only master device is present Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. Master and slave devices are present (2-drives configuration) [Master device] DASP- [Slave device]...
  • Page 167 This page is intentionally left blank.
  • Page 168 CHAPTER 6 OPERATIONS Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. Device Response to the Reset Address Translation Power Save Defect Management...
  • Page 169 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal.
  • Page 170 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.
  • Page 171 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.
  • Page 172 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.
  • Page 173 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.2.1 Default parameters In the logical to physical address translation, the logical cylinder, head, and sector addresses are...
  • Page 174  /RJLFDODGGUHVV )LJXUH $GGUHVVWUDQVODWLRQ H[DPSOHLQ&+6PRGH ...
  • Page 177 CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset.
  • Page 178  6SDUHDUHD  $OWHUQDWLQJGHIHFWLYHVHFWRUV )LJXUH 6HFWRUVOLSSURFHVVLQJ...
  • Page 179 )LJXUH $OWHUQDWHF\OLQGHUDVVLJQPHQW...
  • Page 180 5HDG$KHDG&DFKH  'DWDEXIIHUFRQILJXUDWLRQ )LJXUH 'DWDEXIIHUFRQILJXUDWLRQ...
  • Page 181 6.5.2 Caching operation The caching operation is performed only at receipt of the following commands. The device transfers data from the data buffer to the host system if the following data exist in the data buffer. All sector data to be processed by the command A part of data including the starting sector to be processed by the command When a part of data to be processed exist in the data buffer, the remaining data are read from the disk medium and are transferred to the host system.
  • Page 182 6.5.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases. Miss-hit (no hit) A lead block of the read-requested data is not stored in the data buffer. The requested data is read from the disk media. 1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the sequential address to the last read segment.
  • Page 183 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive tries to fill the buffer space with the read ahead data. a. Sequential command just after non-sequential command At receiving the sequential read command, the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data.
  • Page 184 b. Sequential hit When the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system. The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.
  • Page 185 Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read-ahead operation.
  • Page 186 1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. Partially hit data 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time.
  • Page 187 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.
  • Page 188 At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state.
  • Page 190 #0,/07 422039 472...

This manual is also suitable for:

Mpf3102ahMpf3153ahMpf3104ahMpf3204ah

Table of Contents