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[signal]
[I/O]
IORDY
O
DDMARDY–
O
DSTROBE
O
CSEL
I
DMACK–
I
DMARQ
O
GND
–
Note:
"I" indicates input signal from the host to the device.
"O" indicates output signal from the device to the host.
"I/O" indicates common output or bi-directional signal between the host and the device.
This signal is negated to extend the host transfer cycle of any host
register access (Read or Write) when the device is not ready to respond
to a data transfer request.
DDMARDY– is a flow control signal for Ultra DMA data out bursts.
This signal is asserted by the device to indicate to the host that the
device is ready to receive Ultra DMA data out bursts. The device may
negate DDMARDY– to pause an Ultra DMA data out burst.
DSTROBE is the data in strobe signal from the device for an Ultra
DMA data in burst. Both the rising and falling edge of DSTROBE
latch the data from DATA 0-15 into the host. The device may stop
generating DSTROBE edges to pause an Ultra DMA data in burst.
This signal to configure the device as a master or a slave device.
When CSEL signal is grounded, the IDD is a master device.
When CSEL signal is open, the IDD is a slave device.
This signal is pulled up with 10 k resistor.
The host system asserts this signal as a response that the host system
receive data or to indicate that data is valid.
This signal is used for DMA transfer between the host system and
the device. The device asserts this signal when the device completes
the preparation of DMA data transfer to the host system (at reading)
or from the host system (at writing).
The direction of data transfer is controlled by the IOR- and IOW-
signals. In other word, the device negates the DMARQ signal after
the host system asserts the DMACK– signal. When there is another
data to be transferred, the device asserts the DMARQ signal again.
When the DMA data transfer is performed, IOCW16–, CS0– and
CS1- signals are not asserted. The DMA data transfer is a 16-bit
data transfer. The device has a 10 k pull-down resistor on this
signal.
Grounded
C141-E110-02EN
[Description]
5 - 5
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