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4.6
Read/write Circuit
The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read
circuit, and the time base generator in the read channel (RDC).
4.6.1
Read/write preamplifier (PreAMP)
One PreAMP is mounted on the FPC. The PreAMP consists of a 4-channel read preamplifier and
a write current switch and senses a write error. Each channel is connected to each data head. The
head IC switches the heads by the serial port (SDEN, SCLK, SDATA). The IC generates a write
error sense signal (WUS) when a write error occurs due to head short-circuit or head
disconnection.
4.6.2
Write circuit
The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent
to the encoder circuit in the RDC with synchronizing with the write clock. The NRZ write data is
converted from 48-bits data to 51-bits data by the encoder circuit then sent to the PreAMP, and
the data is written onto the media.
(1)
48/51 GCR
The disk drive converts data using the 48/51 group coded recording (GCR) algorithm.
(2)
Write precompensation
Write precompensation compensates, during a write process, for write non-linearity generated at
reading.
4.6.3
Read circuit
The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit.
Then the output is converted into the sampled read data pulse by the programmable filter circuit
and the FIR adaptation equalizer circuit. This clock signal is converted into the NRZ data by the
48/51 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi
detection circuit, then is sent to the HDC.
(1)
AGC circuit
The AGC circuit automatically regulates the output amplitude to a constant value even when the
input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even
when the head output fluctuates due to the head characteristics or outer/inner head positions.
C141-E110-02EN
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