User's Manual
3.5.3.1 DRAM Timing Selectable
This item allows you to select the DRAM timing value by SPD data or Manual by yourself.
The choices: Manual, By SPD.
3.5.3.2 CAS Latency Time
This item controls the time delay (in clock cycles - CLKs) that passes before the SDRAM
starts to carry out a read command after receiving it. This also determines the number of
CLKs for the completion of the first part of a burst transfer. In other words, the lower the
latency, the faster the transaction.
The choices: 5, 4, 3, 6, Auto.
3.5.3.3 DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS
(Column Address Strobe) signals. This delay occurs when the SDRAM is written to, read
from or refreshed. Naturally, reducing the delay improves the performance of the SDRAM
while increasing it reduces performance.
The choices: 2, 3, 4, 5, 6, Auto.
3.5.3.4 DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its charge before
the SDRAM refreshes. Reducing the precharge time to 2 improves SDRAM performance
but if the precharge time of 2 is insufficient for the installed SDRAM, the SDRAM may not
be refreshed properly and it may fail to retain data
So, for better SDRAM performance, set the SDRAM RAS Precharge Time to 2 but
increase it to 3 if you face system stability issues after reducing the precharge time.
The choices: 2, 3, 4, 5, 6, Auto.
3.5.3.5 Precharge Delay (tRAS)
It allows controlling the memory bank's minimum row active time (tRAS). This constitutes
the time when a row is activated until the time the same row can be deactivated. If the tRAS
period is too long, it can reduce performance by unnecessarily delaying the deactivation of
active rows. Reducing the tRAS period allows the active row to be deactivated earlier.
If the tRAS period is too short, there may not be enough time to complete a burst transfer.
This reduces performance and data may be lost or corrupted.
The choices: Auto, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15.
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