Memory Subsystem - Intel SE7500WV2 Training Manual

Student Workbook

Memory Subsystem

Intel
Memory Subsystem
• Controlled by E7500 MCH
• Registered DDR-200 or 266 ECC
• Provides ECC functions
• Dual memory bus architecture
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The Intel Server Board SE7500WV2 utilizes the Intel E7500 Memory Controller Hub (MCH) to control the memory
subsystem. The MCH includes an integrated memory controller that handles memory I/O requests and provides error
checking and correcting (ECC) functions. The memory controller incorporates two 72-bit-wide memory data paths that
transfer data between the MCH and the DIMMs. This design requires that DIMMs operate in pairs, where a pair consists
of two specific DIMM sockets each of which is connected to a separate memory bus to provide an aggregate 144-bit-
wide memory data path.
DDR memory technology evolved from SDRAM technology. Standard SDRAM transfers data on the rising edge of the
clock cycle; DDR SDRAM transfers data on both the rising and falling edges of the clock cycle, effectively doubling the
data transfer rate to 1.6 GB/s for each of the two memory data paths. Since the memory subsystem utilizes a dual bus
design, the aggregate data transfer rate for the SE7500WV2 memory subsystem is 3.2 GB/s.
The E7500 MCH provides the following ECC functions:
•
Single-bit error correction: If a single-bit error is detected, the ECC logic generates a new "recovered" 64-bit
QWord with a pattern that corresponds to the originally received 8-bit ECC parity code. The corrected data is
returned to the requestor (the processor or PCI master).
•
Multi-bit error detection: Additional errors within the same QWord constitute a multi-bit error, which is
unrecoverable. When a multi-bit memory error is detected, a non-maskable interrupt (NMI) is issued that instructs
the system to shut down to avoid data corruption. Multi-bit errors are very rare.
•
Memory scrubbing: Error correction is performed on data being read from memory. The correction is then passed
to the requestor and at the same time the error is "scrubbed" or corrected in main memory. Memory scrubbing
prevents the accumulation of single-bit errors in main memory that would then become unrecoverable multi-bit
errors.
•
Chip Kill: When x4 memory is installed the ECC function can detect and correct a four-bit error caused by a single
failed memory chip and the system continues to function, though system performance will be affected. When x8
memory is installed the ECC function will detect an eight-bit error caused by a single failed memory chip but will
not be able to correct the error. In this situation a fatal error will be issued.
Guidelines for installing memory in the Intel Server Board SE7500WV2
•
Install only memory modules validated for use with this particular board. Refer to
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All DIMMs within a pair must be identical and must be populated using the pairs DIMM1A:DIMM1B,
DIMM2A:DIMM2B and DIMM3A:DIMM3B
•
DIMMs can be either single- or double-sided and must be a minimum of 128 MB to a maximum of 2 GB in size.
© 2003 Intel Corporation
® Server Board SE7500WV2
SDRAM, 256 MB to 2 GB DIMMs
– Single-bit error correction
– Multi-bit error detection
– Memory scrubbing
– Support for chip kill
– One bank of three 184-pin DIMM
sockets per bus
– Memory must be populated in
pairs
*Other names and brands may be claimed as the property of others.
®
Intel Server Board SE7500WV2 Training
© 2003 Intel Corporation.
http://support.intel.com
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