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Electrical Specifications
Table 3-2. FSB Pin Groups
Signal Group
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
AGTL+ Source Synchronous I/O
AGTL+ Strobes
CMOS Input
Open Drain Output
CMOS Output
CMOS Input
Open Drain Output
FSB Clock
Power/Other
NOTES:
1. Refer to
2. BPM[2:0}# and PRDY# are AGTL+ output only signals.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
3.7
CMOS Signals
CMOS input signals are shown in
signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not
have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals
are required to be asserted for at least three BCLKs in order for the processor to recognize them.
See
Section 3.9
20
Synchronous
to BCLK[1:0]
Synchronous
to BCLK[1:0]
Synchronous
to assoc.
strobe
Synchronous
to BCLK[1:0]
Asynchronous
Asynchronous
Asynchronous
Synchronous
to TCK
Synchronous
to TCK
Clock
Chapter 4
for signal descriptions and termination requirements.
Table
for the DC and AC specifications for the CMOS signal groups.
Type
BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,
TRDY#
ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, PRDY#
Signals
REQ[4:0]#, A[16:3]#
A[31:17]#
D[15:0]#, DINV0#
D[31:16]#, DINV1#
D[47:32]#, DINV2#
D[63:48]#, DINV3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, PWRGOOD, SMI#, SLP#, STPCLK#
FERR#, IERR#, PROCHOT#, THERMTRIP#
PSI#, VID[5:0], BSEL[1:0]
TCK, TDI, TMS, TRST#
TDO
BCLK[1:0], ITP_CLK[1:0]
COMP[3:0], DBR#
THERMDA, THERMDC, V
V
, V
CC_SENSE
SS,
3-2. Legacy output FERR#, IERR# and other non-AGTL+
1
Signals
Associated Strobe
ADSTB[0]#
ADSTB[1]#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
2
2
, GTLREF, RSVD, TEST2, TEST1,
, V
[3:0], V
V
P,
CC
CCA
CC
V
SS_SENSE
[1:0],
Q
CC
Datasheet
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