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Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 5 of 7)
Name
LINT[1:0]
LOCK#
PRDY#
PREQ#
PROCHOT#
PSI#
PWRGOOD
REQ[4:0]#
RESET#
74
Type
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC
Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those
names on the Pentium Processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the
APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the
default configuration.
Input/
LOCK# indicates to the system that a transaction must occur atomically. This
Output
signal must connect the appropriate pins of both FSB agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.
Output
Probe Ready signal used by debug tools to determine processor debug
readiness.
Please refer to the platform design guides for more implementation details.
Input
Probe Request signal used by debug tools to request debug operation of the
processor.
Please refer to the platform design guides for more implementation details.
Output
PROCHOT# (Processor Hot) will go active when the processor temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit
has been activated, if enabled. See
For termination requirements please refer to the platform design guides.
This signal may require voltage translation on the motherboard. Please refer to
the platform design guides for more details.
Output
Processor Power Status Indicator signal. This signal is asserted when the
processor is in a lower state (Deep Sleep and Deeper Sleep). See
for more details.
Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. Clean implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
For termination requirements please refer to the platform design guides.
Input/
REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB
Output
agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[0]#.
Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least two milliseconds after
V
and BCLK have reached their proper specifications. On observing active
CC
RESET#, both FSB agents will deassert their outputs within two clocks. All
processor straps must be valid within the specified setup time before RESET# is
deasserted.
Please refer to the Platform Design Guides for termination requirements and
implementation details. There is a 55 ohm (nominal) on die pullup resistor on this
signal.
Description
Chapter 5
for more details.
Section 2.1.6
Datasheet
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