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Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 7 of 7)
Name
TMS
TRDY#
TRST#
V
CC
V
[3:0]
CCA
V
CCP
V
[1:0]
Q
CC
V
CCSENSE
VID[5:0]
V
SSSENSE
76
Type
Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
Please refer to the platform design guides for termination requirements and
implementation details.
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of both FSB agents.
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. Please refer to the platform design guides for
termination requirements and implementation details.
Input
Processor core power supply.
Input
V
provides isolated power for the internal processor core PLL's. Refer to the
CCA
platform design guides for complete implementation details.
Input
Processor I/O power supply.
Input
Quiet power supply for on die COMP circuitry. These pins should be connected
to V
on the motherboard. However, these connections should enable addition
CCP
of decoupling on the V
Output
V
is an isolated low impedance connection to processor core power
CCSENSE
(V
). It can be used to sense or measure power near the silicon with little noise.
CC
Please refer to the platform design guides for termination recommendations and
more details.
Output
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (Vcc). Unlike some previous generations of processors, these
are CMOS signals that are driven by the Intel
voltage supply for these pins must be valid before the VR can supply Vcc to the
processor. Conversely, the VR output must be disabled until the voltage supply
for the VID pins becomes valid. The VID pins are needed to support the
processor voltage specification variations. See
pins. The VR must supply the voltage that is requested by the pins, or disable
itself.
Output
V
is an isolated low impedance connection to processor core V
SSSENSE
be used to sense or measure ground near the silicon with little noise. Please
refer to the platform design guides for termination recommendations and more
details.
§§
Description
lines if necessary.
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CC
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for definitions of these
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Datasheet
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