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Table 4-5. Signal Description (Sheet 2 of 7)
Name
BSEL[1:0]
COMP[3:0]
D[63:0]#
DBR#
DBSY#
DEFER#
Datasheet
Package Mechanical Specifications and Pin Information
Type
Output
These signals are used to select the FSB clock frequency. They should be
connected between the processor and the chipset MCH and clock generator on
Intel 915 chipset family based platforms. These signals must be left
unconnected on platforms designed with the Intel 855 chipset family. On these
platforms, FSB clock frequency should be configured on the motherboard.
Analog
COMP[3:0] must be terminated on the system board using precision (1%
tolerance) resistors. Refer to the platform design guides for more details on
implementation.
Input/
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
Output
between the FSB agents, and must connect the appropriate pins on both agents.
The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DINV# .
Quad-Pumped Signal Groups
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Furthermore, the DINV# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DINV# signal. When the DINV#
signal is active, the corresponding data group is inverted and therefore sampled
active high.
Output
DBR# (Data Bus Reset) is used only in processor systems where no debug port
is implemented on the system board. DBR# is used by a debug port interposer
so that an in-target probe can drive system reset. If a debug port is implemented
in the system, DBR# is a no connect in the system. DBR# is not a processor
signal.
Input/
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
Output
the FSB to indicate that the data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the appropriate pins on both
FSB agents.
Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or Input/Output agent. This signal must
connect the appropriate pins of both FSB agents.
Description
DSTBN#/
DINV#
DSTBP#
0
0
1
1
2
2
3
3
71
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