Dram Power Info Read Data; Dram Power Limit Data - Intel BX80619I73820 Design Manual

PECI Interface
7.1.2.6.8 DRAM Power Info Read
This read returns the minimum, typical and maximum DRAM power settings and the
maximum time window over which the power can be sustained for the entire DRAM
domain and is inclusive of all the DIMMs within all the memory channels. Any power
values specified by the power limiting entity that is outside of the range specified
through these settings cannot be guaranteed. Since this data is 64 bits wide, PECI
facilitates access to this register by allowing two requests to read the lower 32 bits and
upper 32 bits separately as shown in
defined as per the Package Power SKU Unit settings described in
Figure 7-16. DRAM Power Info Read Data
63 55
Reserved
31 30
Reserved Minimum DRAM Power
7.1.2.6.9 DRAM Power Limit Data Write / Read
This feature allows the PECI host to program the power limit over a specified time or
control window for the entire DRAM domain covering all the DIMMs within all the
memory channels. Actual values are chosen based on DRAM power consumption
characteristics. The units for the DRAM Power Limit and Control Time Window are
determined as per the Package Power SKU Unit settings described in
The DRAM Power Limit Enable bit in
Figure 7-17. DRAM Power Limit Data
3 1 24 2 3
R ES ER VED
7.1.2.6.10 DRAM Power Limit Performance Status Read
This service allows the PECI host to assess the performance impact of the currently
active DRAM power limiting modes. The read return data contains the sum of all the
time durations for which each of the DIMMs has been operating in a low power state.
This information is tracked by a 32-bit counter that wraps around. The unit for time is
determined as per the Package Power SKU Unit settings described in
Thermal/Mechanical Specifications and Design Guide
54 48
Maximum Time
Window
DRAM_POWER_INFO (upper bits)
DRAM_POWER_INFO (lower bits)
17 1 6
C o ntrol Tim e
R ES ER V ED
W in dow
D R A M _ PO W ER _ LIM IT D ata
Table 7-6. Power and time units for this read are
47 46
Reserved Maximum DRAM Power
16 15 14
Reserved
Figure 7-17 should be set to activate this feature.
1 4
15
D R A M
Pow er Lim it
Enable
Section 7.1.2.7.
32
TDP DRAM Power
(Typical Value)
Section 7.1.2.7.
D R A M Pow er Lim it
Section 7.1.2.7.
0
0
67