Rdpciconfig(); Pci Configuration Address - Intel BX80619I73820 Design Manual

Table 7-12. RdIAMSR() Services Summary (Sheet 2 of 2)
Processor MSR
ID Address
(byte) (dword)
0x0-0xF 0x040B IA32_MC2_MISC
0x0-0xF 0x040C IA32_MC3_CTL
0x0-0xF 0x0283 IA32_MC3_CTL2
0x0-0xF 0x040D IA32_MC3_STATUS
0x0-0xF 0x040E IA32_MC3_ADDR
0x0-0xF 0x040F IA32_MC3_MISC
0x0-0xF 0x0410 IA32_MC4_CTL
0x0-0xF 0x0284 IA32_MC4_CTL2
0x0-0xF 0x0411 IA32_MC4_STATUS
0x0-0xF 0x0412 IA32_MC4_ADDR
0x0-0xF 0x0413 IA32_MC4_MISC
0x0-0xF 0x0414 IA32_MC5_CTL
0x0-0xF 0x0285 IA32_MC5_CTL2
0x0-0xF 0x0415 IA32_MC5_STATUS
0x0-0xF 0x0416 IA32_MC5_ADDR
0x0-0xF 0x0417 IA32_MC5_MISC
0x0-0xF 0x0418 IA32_MC6_CTL
0x0-0xF 0x0286 IA32_MC6_CTL2
0x0-0xF 0x0419 IA32_MC6_STATUS
0x0-0xF 0x041A IA32_MC6_ADDR
7.1.4.10

RdPCIConfig()

The RdPCIConfig() command provides sideband read access to the PCI configuration
space maintained in downstream devices external to the processor. The exact listing of
supported devices, functions and registers can be found in the relevant sections of the
Intel
originators may conduct a device/function/register enumeration sweep of this space by
issuing reads in the same manner that the BIOS would. A response of all 1s may
indicate that the device/function/register is unimplemented even with a 'passing'
completion code. Responses will follow normal PCI protocol.
PCI configuration addresses are constructed as shown in
band procedures, the Bus number would be used to direct a read or write to the proper
device. All accesses to Bus0, Device[0-7] and Bus1, Device[8-15] are decoded to
registers within the processor while the remaining accesses are decoded to registers in
downstream devices.
Figure 7-39. PCI Configuration Address
31 28 27
Reserved
82
Processor
Meaning ID
(byte)
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
0x0-0xF
®
Core™ i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 2. PECI
20 19
Bus
MSR
Address Meaning
(dword)
0x0426 IA32_MC9_ADDR
0x0427 IA32_MC9_MISC
0x0428 IA32_MC10_CTL
0x028A IA32_MC10_CTL2
0x0429 IA32_MC10_STATUS 0x0-0xF
0x042A IA32_MC10_ADDR
0x042B IA32_MC10_MISC
0x042C MC11_CTLIA32_
0x028B IA32_MC11_CTL2
0x042D IA32_MC11_STATUS 0x0-0xF
0x042E IA32_MC11_ADDR
0x042F IA32_MC11_MISC
0x0430 IA32_MC12_CTL
0x028C IA32_MC12_CTL2
0x0431 IA32_MC12_STATUS 0x0-0xF
0x0432 IA32_MC12_ADDR
0x0433 IA32_MC12_MISC
0x0434 IA32_MC13_CTL
0x028D IA32_MC13_CTL2
0x0435 IA32_MC13_STATUS
15 14 12 11
Device Function
Thermal/Mechanical Specifications and Design Guide
PECI Interface
Processor MSR
ID Address
(byte) (dword)
0x0-0xF 0x0441 IA32_MC16_STATUS
0x0-0xF 0x0442 IA32_MC16_ADDR
0x0-0xF 0x0443 IA32_MC16_MISC
0x0-0xF 0x0444 IA32_MC17_CTL
0x0291 IA32_MC17_CTL2
0x0-0xF 0x0445 IA32_MC17_STATUS
0x0-0xF 0x0446 IA32_MC17_ADDR
0x0-0xF 0x0447 IA32_MC17_MISC
0x0-0xF 0x0448 IA32_MC18_CTL
0x0292 IA32_MC18_CTL2
0x0-0xF 0x0449 IA32_MC18_STATUS
0x0-0xF 0x044A IA32_MC18_ADDR
0x0-0xF 0x044B IA32_MC18_MISC
0x0-0xF 0x044C IA32_MC19_CTL
0x0293 IA32_MC19_CTL2
0x0-0xF 0x044D IA32_MC19_STATUS
0x0-0xF 0x044E IA32_MC19_ADDR
Figure 7-39. Under normal in-
Register
Meaning
0