HP 37717C Calibration Manual page 37

General Information
Specifications
700 kb/s to 170 Mb/s (ECL)
Format: NRZ
Source impedance: Nominal TTL into
75 to ground or nominal ECL
into75 to -2V
Return loss: Typically >15 dB, 500
kHz to 100 MHz (TTL)
Binary Clock Output
Clock rates: 700 kb/s to 50 Mb/s
(TTL), 700 kb/s to 170 Mb/s (ECL)
Format: Nominal squarewave 60/40 to
40/60 duty cycle.
Source impedance: Nominal TTL into
75 to ground or nominal ECL into
75 to -2V
Return loss: Typically >10 dB, 500
kHz to 100 MHz (TTL)
External Clock Input
Clock rates: 700 kb/s to 50 Mb/s
(TTL), 700 kb/s to 170 Mb/s (ECL)
Logic threshold:1.5V (TTL), -1.3V
(ECL), ground (0V), signal mean level.
Termination: Nominal TTL into 75
to ground or nominal ECL into75
-2V
Format: Nominal squarewave 60/40 to
40/60 duty cycle.
Return loss: Typically >15 dB, 500
kHz to 200 MHz (TTL)
Receiver
Binary Data Input
Data rates: 700 kb/s to 50 Mb/s (TTL),
700 kb/s to 170 Mb/s (ECL)
Logic threshold:1.5V (TTL), -1.3V
(ECL), ground (0V).
Format: NRZ
Termination: Nominal TTL into 75
to ground or nominal ECL into75
2V
1-16
Return loss: Typically >15 dB, 500
kHz to 200 MHz (TTL)
Binary Clock Input
Clock rates: 700 kb/s to 50 Mb/s
(TTL), 700 kb/s to 170 Mb/s (ECL)
Logic threshold:1.5V (TTL), -1.3V
(ECL), ground (0V), signal mean level.
Format: Nominal squarewave 60/40 to
40/60 duty cycle.
Termination: Nominal TTL into 75
to ground or nominal ECL into75
-2V
Return loss: Typically >15 dB, 500
kHz to 100 MHz (TTL)
Binary interface rates: 2, 8, 34 and
140 Mb/s if Option UKJ is fitted. 0.7, 2,
8, 34and 140 Mb/s if Option UKK is
fitted.
Frequency measurement: On
external clock input and binary clock
input.
Jitter generation: Simultaneous jitter
of binary clock and binary data outputs
to
if Option UHK or A3K (2, 8, 34 & 140
Mb/s) is fitted.
Jitter measurement: Jitter
measurement of binary clock input if
Option UHN, A1M, A1N, A1P, A3L,
A3V or A3N (2, 8, 34 & 140 Mb/s
100 ppm) is fitted.
to -
to