L2 Cache Ecc Mode; Init # Upon Shutdown Cycle; Pci Configuration - Intergraph StudioZ GT RAX Setup Manual

Parity Error Signal
When this option is enabled, parity errors halt the operating system. The default setting is
Enabled.
Report Receive Data Parity Errors
Enable this option to cause the system to generate parity errors when bad receive data parity is
detected. The default setting is Enabled.

L2 Cache ECC Mode

This option enables the use of correction logic on cache reads. If disabled, data read from cache is
supplied unaltered to the CPU. The default setting is Disabled.

INIT # Upon Shutdown Cycle

When enabled, the chipset asserts INIT# upon receiving a shutdown command. The default setting
is Enabled.

PCI Configuration

Use this option to display a submenu with options for configuring IRQs for legacy ISA devices:
PCI Device, Embedded SCSI A
This option displays choices for configuring the features of embedded SCSI device A.
Entry
Onboard LVD SCSI
Controller
Option ROM Scan
Enable Master
Latency Timer
PCI INTA IRQ Mapping
Description
Controls whether or not the system activates the embedded PCI
device. The default setting is Enabled.
Initializes device expansion ROM. The default setting is Enabled.
Enables the selected device as a PCI bus master. The default
setting is Enabled.
Sets the minimum guaranteed time slice allotted for the bust
master in units of PCI bus clocks. The default setting is 0040H.
Devices can use hardware interrupts called IRQs. A PCI device
cannot use IRQs that are already in use by ISA devices. Use Auto
only if no ISA legacy cards are installed. The default setting is
Auto-select.
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