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BG60.
Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled
Breakpoints
Problem:
When a debug exception is signaled on a load that crosses cache lines with data
forwarded from a store and whose corresponding breakpoint enable flags are disabled
(DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.
Implication: The debug exception DR6.B0-B3 flags may be incorrect for the load if the
corresponding breakpoint enable flag in DR7 is disabled.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG61.
Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write
Major Mode Enabled
Problem:
Under a specific set of conditions, critical ISOCH (isochronous) traffic may cause
unpredictable system behavior with write major mode enabled.
Implication: Due to this erratum unpredictable system behavior may occur.
Workaround:Write major mode must be disabled in the BIOS by writing the write major mode
threshold value to its maximum value of 1FH in ISOCHEXITTRESHOLD bits [19:15],
ISOCHENTRYTHRESHOLD
WMEXITTHRESHOLD bits [4:0] of the MC_CHANNEL_{0,1,2}_WAQ_PARAMS register.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG62.
A String Instruction that Re-maps a Page May Encounter an Unexpected Page
Fault
Problem:
An unexpected page fault (#PF) may occur for a page under the following conditions:
Implication: Software may see an unexpected page fault that indicates that there is no translation
for the page. Intel has not observed this erratum with any commercially-available
software or system.
•
The paging structures initially specify a valid translation for the page.
•
Software modifies the paging structures so that there is no valid translation for the
page (e.g., by clearing to 0 the present bit in one of the paging-structure entries
used to translate the page).
•
An iteration of a string instruction modifies the paging structures so that the
translation is again a valid translation for the page (e.g., by setting to 1 the bit that
was cleared earlier).
•
A later iteration of the same string instruction loads from a linear address on the
page.
•
Software did not invalidate TLB entries for the page between the first modification
of the paging structures and the string instruction. In this case, the load in the later
iteration may cause a page fault that indicates that there is no translation for the
page (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was
caused by a not-present page).
Workaround:Software should not update the paging structures with a string instruction that
accesses pages mapped the modified paging structures.
Status:
For the steppings affected, see the Summary Tables of Changes.
38
bits
[14:10],
WMENTRYTHRESHOLD
Errata
bits
[9:5],
and
Specification Update
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