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BG35.
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a
System Hang
Problem:
Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a
system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in
another machine check bank (IA32_MCi_STATUS).
Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang
and an Internal Timer Error to be logged.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG36.
IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
Problem:
The IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [34:32] may be incorrectly set to 7H
after reset; the correct value should be 0H.
Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset
(EN_FIXED_CTR{0, 1, 2} may be enabled).
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG37.
Performance Monitor Counter INST_RETIRED.STORES May Count Higher Than
Expected
Problem:
Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track
retired instructions which contain a store operation. Due to this erratum, the processor
may also count other types of instructions including WRMSR and MFENCE.
Implication: Performance Monitoring counter INST_RETIRED.STORES may report counts higher than
expected.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG38.
Sleeping Cores May Not Be Woken up on Logical Cluster Mode Broadcast IPI
Using Destination Field Instead of Shorthand
Problem:
If software sends a logical cluster broadcast IPI using a destination shorthand of 00B
(No Shorthand) and writes the cluster portion of the Destination Field of the Interrupt
Command Register to all ones while not using all 1s in the mask portion of the
Destination Field, target cores in a sleep state that are identified by the mask portion of
the Destination Field may not be woken up. This erratum does not occur if the
destination shorthand is set to 10B (All Including Self) or 11B (All Excluding Self).
Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle
the broadcast IPI. Intel has not observed this erratum with any commercially-available
software.
Workaround:Use destination shorthand of 10B or 11B to send broadcast IPIs.
Status:
For the steppings affected, see the Summary Tables of Changes.
30
Errata
Specification Update
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