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BG42.
Performance Monitor Counters May Count Incorrectly
Problem:
Under certain circumstances, a general purpose performance counter, IA32_PMC0-4
(C1H - C4H), may count at core frequency or not count at all instead of counting the
programmed event.
Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed
event. Due to the requirements of the workaround there may be an interruption in the
counting of a previously programmed event during the programming of a new event.
Workaround:Before programming the performance event select registers, IA32_PERFEVTSELx MSR
(186H - 189H), the internal monitoring hardware must be cleared. This is accomplished
by first disabling, saving valid events and clearing from the select registers, then
programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the
IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and
restoring previous programming if necessary. Each performance counter, IA32_PMCx,
must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of
the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits
[3:0].
All
IA32_PERFEVTSELx MSRs before programming the performance counters. Note that
the performance counter will not increment when its IA32_PERFEVTSELx MSR has a
value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK
field (bits [15:8]).
Status:
For the steppings affected, see the Summary Tables of Changes.
BG43.
Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT
Stores to Local DRAM Correctly
Problem:
When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0
event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is
counted. The following two selections do not provide accurate counts when counting NT
(Non-Temporal) Stores:
•
OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
•
OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is
set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have
been.
Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
32
three
values
must
be
written
to
either
Errata
the
same
or
different
Specification Update
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