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BG3.
Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address onto the
Stack
Problem:
Normally, when the processor encounters a Segment Limit or Canonical Fault due to
code execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher
priority
break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a non-
canonical address, the address pushed onto the stack for this #GP fault may not match
the non-canonical address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commercially-
available software.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG4.
Performance Monitor SSE Retired Instructions May Return Incorrect Values
Problem:
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track
retired SSE instructions. Due to this erratum, the processor may also count other types
of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than
expected.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
18
Interrupt
or
Exception
(e.g.,
NMI
(Non-Maskable
Errata
Interrupt),
Debug
Specification Update
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