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BG54.
DPRSLPVR Signal May Be Incorrectly Asserted on Transition between Low
Power C-states
Problem:
On entry to or exit from package Deep Power Down Technology (code name C6 state)
states, DPRSLPVR (Deeper Sleep Voltage Regulator) signal may be incorrectly asserted.
Implication: Due to this erratum, platform voltage regulator may shutdown
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG55.
Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
Problem:
Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA
should only increment the count when a load is blocked by a store. Due to this erratum,
the count will be incremented whenever a load hits a store, whether it is blocked or can
forward. In addition this event does not count for specific threads correctly.
Implication: If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events
STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence
of loads blocked by stores than have actually occurred. If Intel Hyper-Threading
Technology is enabled, the counts of loads blocked by stores may be unpredictable and
they could be higher or lower than the correct count.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG56.
Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem:
When a performance monitoring counter is configured for PEBS (Precise Event Based
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS
buffer. The information in the PEBS record represents the state of the next instruction
to be executed following the counter overflow. Due to this erratum, if the counter
overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is
delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record being
delayed by one instruction following execution of MOV SS or STI. The state information
in the PEBS record will also reflect the one instruction delay.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
36
Errata
Specification Update
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