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BG23.
The Memory Controller tTHROT_OPREF Timings May Be Violated during Self-
Refresh Entry
Problem:
During self-refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING
CSR).
Implication: The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG24.
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does
Not Work
Problem:
When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously
reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both
MSRs increment and overflow independently.
Implication: Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG25.
Disabling Thermal Monitor While Processor Is Hot, Then Re-enabling, May
Result in Stuck Core Operating Ratio
Problem:
If a processor is at its TCC (Thermal Control Circuit) activation temperature and then
Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a
subsequent re-enable of Intel Thermal Monitor will result in an artificial ceiling on the
maximum core P-state. The ceiling is based on the core frequency at the time of Intel
Thermal Monitor disable. This condition will only correct itself once the processor
reaches its TCC activation temperature again.
Implication: Since Intel requires that Intel Thermal Monitor be enabled in order to be operating
within specification, this erratum should never be seen during normal operation.
Workaround:Software should not disable Intel Thermal Monitor during processor operation.
Status:
For the steppings affected, see the Summary Tables of Changes.
26
Errata
Specification Update
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