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Errata
BG77.
PCI Express Cards May Not Train to x16 Link Width
Problem:
The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1;
Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8,
even though the processor may actually be capable of supporting the full x16 width.
Implication: Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express
CLB (Compliance Load Board) Cards used during PCI Express Compliance mode testing
may only train to x8 link width.
Workaround:A BIOS workaround has been identified. .
Status:
For the steppings affected, see the Summary Tables of Changes.
BG78.
The APIC Timer Current Count Register May Prematurely Read 0x0 While the
Timer Is Still Running
Problem:
The APIC Timer Current Counter Register may prematurely read 0x00000000 while the
timer is still running. This problem occurs when a core frequency or C-state transition
occurs while the APIC timer countdown is in progress.
Implication: Due to this erratum, certain software may incorrectly assess that the APIC timer
countdown is complete when it is actually still running. This erratum does not affect the
delivery of the timer interrupt.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BG79.
CKE May go Low Within tRFC(min) After a PD Exit
Problem:
After a refresh command is issued, followed by an early PD (Power Down) Entry and
Exit, the CKE (Clock Enable) signal may be asserted low prior to tRFC(min), the
Minimum Refresh Cycle timing. This additional instance of CKE being low causes the
processor not to meet the JEDEC DDR3 DRAM specification requirement (Section
4.17.4 Power-Down clarifications - Case 3).
Implication: Due to this erratum, the processor may not meet the JEDEC DDR3 DRAM specification
requirement that states: "CKE cannot be registered low twice within a tRFC(min)
window". Intel has not observed any functional failure due to this erratum.
Workaround:None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
43
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