Mii Management Configuration Register - Digi NS9750 Hardware Reference Manual

MII Management Configuration register

Address: A060 0420
31
15
RMIIM
Register bit assignment
Bits
D31:16
D15
D14:05
D04:02
D01
D00
Table 218: MII Management Configuration register
30 29 28 27
14 13 12 11
Access Mnemonic
N/A Reserved
R/W RMIIM
N/A Reserved
R/W CLKS
R/W SPRE
R/W Not used
E t h e r n e t C o m m u n i c a t i o n M o d u l e
26 25 24 23
Reserved
10 9 8 7
Reserved
Reset Description
N/A N/A
0 Reset MII management block
Set this bit to 1 to reset the MII Management module.
N/A N/A
0x0 Clock select
Used by the clock divide logic in creating the MII
management clock, which (per the IEEE 802.3u
standard) can be no faster than 2.5 MHz.
Note:
The AHB bus clock is used as the input to the clock
divide logic. "Clocks field settings," on page 360,
shows the settings that are supported.
0 Suppress preamble
0 Causes normal cycles to be performed
1 Causes the MII Management module to perform
read/write cycles without the 32-bit preamble
field. (Preamble suppression is supported by
some PHYs.)
0 Always write to 0.
w w w . d i g i e m b e d d e d . c o m
22 21 20 19
6 5 4 3
CLKS
Some PHYs support clock rates up to 12.5
MHz.
18 17 16
2 1 0
Not
SPRE
used
3 5 9