Serial Port Performance; Serial Port Control And Status Registers - Digi NS9750 Hardware Reference Manual

Single chip 0.13μm cmos network-attached processor

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S e r i a l p o r t p e r f o r m a n c e

To facilitate an interrupt when either the RRDY or RBC status bits are active, the

processor must set one or both of the corresponding interrupt enables in Serial

Channel B/A/C/D Control Register A.

Using the DMA controller

When using DMA, the processor need not interface with any of the serial port

registers for data flow; rather, the processor must interface with the DMA channel

registers and the DMA buffer descriptor block. To facilitate use of transmit DMA, the

ERXDMA field in Serial Channel B/A/C/D Control register A must be set active high.

When ERXDMA is set active high, disable the serial receiver interrupts.

Serial port performance

The serial ports have a finite performance limit on their ability to handle various

serial protocols. The performance is limited by the speed of the SYSCLK operating the

NS9750 ASIC. The configured speed for the internal PLL defines the BCLK rate; for

UART (x8), the serial port maximum rate is 1834200 baud, for UART (x16), the serial

port maximum rate is 921600 baud, and for UART (x32), the serial port maximum rate

is 460800 baud.

The configuration registers for serial controller B are located at

configuration registers for serial controller A are located at

shows a single, two-channel address map for serial controllers B and A.

All configuration registers must be accessed as 32-bit words and as single accesses

only. Bursting is not allowed.

Table 365: Serial channel B & A configuration registers

Channel B Control Register A

Channel B Control Register B

N S 9 7 5 0 H a r d w a r e R e f e r e n c e

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