Static Memory Controller; More Information - Digi NS9750 Hardware Reference Manual

Single chip 0.13μm cmos network-attached processor

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Static memory controller

Table 48 shows configurations for the static memory controller with different types of

memory devices. See "Static Memory Configuration 0–3 registers" on page 230 for

Page mode ROM

Extended wait ROM

Page mode SRAM

Extended wait SRAM

Page mode flash

Extended wait flash

Memory mapped peripheral

Enabling the buffers means that any access causes the buffer to be used. Depending on the

application, this can provide performance improvements. Devices without async-page-mode

support generally work better with the buffer disabled. Again, depending on the application, this

can provide performance improvements.

SRAM and Flash memory devices can be write-protected if required.

Buffering must be disabled when performing Flash memory commands and during writes.

Table 48: Static memory controller configurations

Buffering enables the transaction order to be rearranged to improve

memory performance. If the transaction order is important, the buffers

must be disabled.

Extended wait and page mode cannot be enabled at the same time.

Write protect

Disabled (or enabled)

Disabled or (enabled)

Disabled (or enabled)

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