Pci Arbiter Functional Description - Digi NS9750 Hardware Reference Manual

NS9750 can be configured to use either the embedded PCI arbiter or an external
arbiter through the bootstrap initialization scheme used during powerup (see
"Bootstrap initialization" on page 272). The
The internal arbiter is used if
If a pulldown resistor is placed on the
When an external arbiter is used, the
the internal PCI-to-AHB bridge are brought to external pins on NS9750 (see
Figure 73, "System connections to NS9750 — External arbiter and central
resources," on page 457).

PCI arbiter functional description

The PCI bus arbiter supports up to four PCI masters, including the PCI-to-AHB bridge,
using the rotating priority scheme shown in Table 258. With rotating priority, the
priority of a master depends on its relative position to the last granted master. After
reset, the arbiter defaults to the PCI-to-AHB bridge having the highest priority.
Last granted
master
PCI-to-AHB
bridge
External master
1
External master
2
External master
3
Table 258: Rotating priority scheme
Each master has a set of
its
REQ#
to the requester with the highest priority. Until the bus is idle (that is,
are both inactive), the arbiter continually arbitrates and the asserted
IRDY#
change each clock cycle. One
being asserted in this situation. When the bus goes idle, the arbiter stops arbitrating
and the master with the asserted
Highest
priority
External master
1
External master
2
External master
3
PCI-to-AHB
bridge
REQ#/GNT#
when it needs to execute a bus transaction. The arbiter then asserts the
pin selects the source of the arbiter:
RTCK
.
RTCK = 1
bit, an external arbiter is used.
RTCK
REQ#/GNT#
nd rd
2 priority 3 priority
External master External master
2 3
External master PCI-to-AHB
3 bridge
PCI-to-AHB External master
bridge 1
External master External master
1 2
signals used for bus arbitration. The master asserts
can be negated coincident with another
GNT#
is allowed to start a transaction.
GNT#
w w w . d i g i e m b e d d e d . c o m
P C I - t o - A H B B r i d g e
(request/grant) signals for
Lowest Parked
priority master
PCI-to-AHB PCI-to-AHB
bridge bridge
External master External master
1 1
External master External master
2 2
External master External master
3 3
FRAME#
GNT#
and
can
GNT#
GNT#
4 1 9