Page 1 NS9750 Hardware Reference 90000624_G...
Page 3 NS9750 Hardware Reference Part number/version: 90000624_G Release date: March 2008 www.digiembedded.com...
Page 4 Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of, fitness or merchantability for a particular purpose. Digi may make improvements and/or changes in this manual or in the product(s) and/or the program(s) described in this manual at any time.
Page 5: Table Of Contents
Contents C h a p t e r 1 : A b o u t N S 9 7 5 0 NS9750 Features ... 2 System-level interfaces... 8 System boot ... 10 Reset... 10 RESET_DONE as an input... 11 RESET_DONE as an output ... 11 System clock...
Page 6 C h a p t e r 3 : W o r k i n g w i t h t h e C P U About the processor ... 48 Instruction sets... 49 System control processor (CP15) registers... 51 Jazelle (Java) ...
Page 7 TLB structure ...104 Caches and write buffer ...105 Cache features ...105 Write buffer ...106 Enabling the caches ...107 Cache MVA and Set/Way formats ...109 Noncachable instruction fetches ...111 Self-modifying code ...112 AHB behavior ...112 Instruction Memory Barrier...113 IMB operation...113 Sample IMB sequences ...114 C h a p t e r 4 : S y s t e m C o n t r o l M o d u l e System Control Module features ...116 Bus interconnection ...116...
Page 8 C h a p t e r 5 : M e m o r y C o n t r o l l e r Features...178 Static memory controller...183 Interrupt Status Raw ...152 Timer Interrupt Status register ...153 Software Watchdog Configuration register ...153 Software Watchdog Timer register ...155 Clock Configuration register ...155 Reset and Sleep Control register ...157...
Page 9 Dynamic memory controller ...224 Write protection ...224 Access sequencing and memory width ...224 Address mapping ...225 Registers ...264 Register map ...264 Reset values ...266 Control register ...267 Status register...269 Configuration register...269 Dynamic Memory Control register...270 Dynamic Memory Refresh Timer register ...272 Dynamic Memory Read Configuration register ...274 Dynamic Memory Precharge Command Period register ...275 Dynamic Memory Active to Precharge Command Period register ...276...
Page 10 Overview ...316 Ethernet MAC...317 Ethernet front-end module ...323 External CAM filtering ...334 Ethernet Control and Status registers ...337 viii Station address logic (SAL) ...321 Statistics module ...321 Receive packet processor ...324 Transmit packet processor ...327 Ethernet Slave Interface...330 Interrupts ...331 Resets...332 Ethernet General Control Register #1 ...339 Ethernet General Control Register #2 ...342...
Page 11 PCI arbiter functional description...419 Slave interface ...420 PCI Arbiter Configuration registers ...420 PCI system configurations ...456 Device selection for configuration ...458 PCI interrupts...458 PCI central resource functions...458 CardBus Support ...461 Configuring NS9750 for CardBus support ...463 CardBus adapter requirements ...464 ... 403...
Page 12 C h a p t e r 8 : B B u s B r i d g e BBus bridge functions ...468 Bridge control logic ...469 BBus control logic ...472 Two-channel AHB DMA controller (AHB bus) ...474 Interrupt aggregation ...483 Bandwidth requirements ...483 SPI-EEPROM boot logic ...484 BBus Bridge Control and Status registers ...490...
Page 13 DMA buffer descriptor ...504 DMA channel assignments ...509 DMA Control and Status registers ...510 DMA Buffer Descriptor Pointer...512 DMA Control register ...514 DMA Status/Interrupt Enable register ...516 C h a p t e r 1 0 : B B u s U t i l i t y BBus Utility Control and Status registers ...522 Master Reset register...523 GPIO Configuration registers ...524...
Page 14 Flow charts ...556 C h a p t e r 1 2 : L C D C o n t r o l l e r LCD features...560 LCD controller functional overview...564 AHB interface ...568 Registers ...579 Master module (normal mode, 16-bit)...556 Slave module (normal mode, 16-bit) ...557 ...559 Programmable parameters ...560...
Page 15 LCDPalette register...595 Interrupts ...598 MBERRORINTR — Master bus error interrupt...598 VCOMPINTR — Vertical compare interrupt...598 LBUINTR — Next base address update interrupt ...599 C h a p t e r 1 3 : S e r i a l C o n t r o l M o d u l e : U A R T Features...602 Bit-rate generator ...603 UART mode ...604...
Page 16 Serial port control and status registers ...650 C h a p t e r 1 5 : I E E E 1 2 8 4 P e r i p h e r a l C o n t r o l l e r Requirements ...670 Overview ...670 BBus slave and DMA interface ...677...
Page 17 Pin Interrupt Mask register ...700 Pin Interrupt Control register...701 Granularity Count register ...702 Forward Address register ...703 Core Phase (IEEE1284) register ...704 C h a p t e r 1 6 : U S B C o n t r o l l e r M o d u l e Overview ...708 USB module architecture ...708 USB device block...710...
Page 18 USB Device Block registers ...765 USB Device Endpoint FIFO Control and Data registers ...767 C h a p t e r 1 7 : T i m i n g Electrical characteristics ...788 DC electrical characteristics ...790 Reset and edge sensitive input timing requirements ...792 Power sequencing ...794 HcHCCA register ...739 HcPeriodCurrentED register ...740...
Page 19 Ethernet MII timing ...814 Ethernet RMII timing ...815 PCI timing ...816 Internal PCI arbiter timing ...818 PCI burst write from NS9750 timing ...818 PCI burst read from NS9750 timing ...819 PCI burst write to NS9750 timing...819 PCI burst read to NS9750 timing...820 PCI clock timing ...820...
Page 20 IEEE 1284 timing ...831 USB timing ...832 Reset and hardware strapping timing ...835 JTAG timing ...836 Clock timing ...837 C h a p t e r 1 8 : P a c k a g i n g xviii SPI master mode 0 and 1: 2-byte transfer ...829 SPI master mode 2 and 3: 2-byte transfer ...829 SPI slave mode 0 and 1: 2-byte transfer ...830 SPI slave mode 2 and 3: 2-byte transfer ...830...
Page 21: About This Guide
90000623_E). A single PDF (90000624_E) is included on your documentation CD. About this guide This guide provides information about the Digi NS9750, a single chip 0.13μm CMOS network-attached processor. The NS9750 is part of the Digi NET+ARM family of devices.
Page 22 NS9750 key features NS9750 ball grid array assignments NS9750 CPU System functionality How the NS9750 works with the Multiport Memory Controller, an AMBA-compliant SoC peripheral How the NS9750 works with Ethernet MAC and Ethernet front-end module PCI-to-AHB bus functionality, which connects PCI-...
Page 23: Conventions Used In This Guide
‘d ‘h RW1TC Related documentation NS9750 Jumpers and Components provides a hardware description of the NS9750 development board, and includes information about jumpers, components, switches, and configuration. NS9750 Sample Driver Configurations provides sample configurations that you can use to develop your drivers.
Page 24: Customer Support
Be aware that if you see differences between the documentation you received in your package and the documentation on the Web site, the Web site content is the latest version. Customer support To get help with a question or technical problem with this product, or to make comments and recommendations about our products or documentation, use the contact information listed in this table: Technical support...
Page 25 About NS9750 he Digi NS9750 is a single chip 0.13μm CMOS network-attached processor. This chapter provides an overview of the NS9750, which is based on the standard architecture in the NET+ARM family of devices.
Page 26: Ns9750 Features
Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard architecture. The NS9750 runs up to 200 MHz, with a 100 MHz system and memory bus and 50 MHz peripheral bus. The NS9750 offers an extensive set of I/O interfaces and Ethernet high-speed performance and processing capacity.
Page 27 Burst mode support with automatic data width adjustment Two external DMA channels for external peripheral support System Boot High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending) High performance 10/100 Ethernet MAC 10/100 Mbps MII/RMII PHY interfaces Full-duplex or half-duplex...
Page 28 N S 9 7 5 0 F e a t u r e s Flexible LCD controller Supports most commercially available displays: Active Matrix color TFT displays: – Up to 24bpp direct 8:8:8 RGB; 16 colors Single and dual panel color STN displays: –...
Page 29 Internal or external clock support, digital PLL for RX clock extraction 4 receive-side data match detectors 2 dedicated DMA channels per module, 8 channels total 32 byte TX FIFO and 32 byte RX FIFO per module C port C v.1.0 configurable to master or slave mode Bit rates: fast (400 kHz) or normal (100 kHz) with clock stretching 7-bit and 10-bit address modes Supports I...
Page 30 N S 9 7 5 0 F e a t u r e s Each DMA channel supports memory-to-memory transfers Power management (patent pending) Power save during normal operation Disables unused modules – Power save during sleep mode Sets memory controller to refresh –...
Page 31 External interrupts 4 external programmable interrupts Rising or falling edge-sensitive – Low level- or high level-sensitive – Clock generator Low cost external crystal On-chip phase locked loop (PLL) Software programmable PLL parameters Optional external oscillator Separate PLL for USB Operating grades/Ambient temperatures 200 MHz: 0 –...
Page 32: System-Level Interfaces
S y s t e m - l e v e l i n t e r f a c e s System-level interfaces Figure 1 shows the NS9750 system-level interfaces. GPIO Figure 1: System-level hardware interfaces Ethernet MII/RMII interface to external PHY...
Page 33 1284 port – Up to 24-bit TFT or STN color and monochrome LCD controller – Two external DMA channels – Four external interrupt pins programmed to rising or falling edge, or to high – or low level Sixteen 16-bit or 32-bit programmable timers or counters –...
Page 34: System Boot
Figure 2: Two methods of booting NS9750 system Reset Master reset using an external reset pin resets NS9750. Only the AHB bus error status registers retain their values; software read resets these error status registers. The N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 35: Reset_Done As An Input
input reset pin can be driven by a system reset circuit or a simple power-on reset circuit. RESET_DONE as an input Used at bootup only: When set to 0, the system boots from SDRAM through the serial SPI EEPROM. When set to 1, the system boots from Flash/ROM. This is the default. RESET_DONE as an output Sets to 1, per Step 6 in the boot sequence.
Page 36 Figure 3: Sample reset circuit You can use one of five software resets to reset the NS9750. Select the reset by setting the appropriate bit in the appropriate register. Watchdog timer can issue reset upon watchdog timer expiration (see "Software Watchdog Timer register"...
Page 37: System Clock
Table 2: Sample clock frequency settings with 29.4912 MHz crystal If an oscillator is used, it must be connected to the NS9750. If a crystal is used, it must be connected with a circuit such as the one shown in Figure 4.
Page 38 . For a 200 MHz grade, then, the CPU may change from on pin T3 for receive clock and rx_clk , should be tied low. tx_clk S_PLL_BP_ GPIO19_PLL_BP 2R4K NS9750 X1_SYS X1_SYS_OSC X2_SYS X2_SYS_OSC 330 OHM on pin V3 for tx_clk...
Page 39: Usb Clock
“low impedance” for the 16 MHz oscillation to ground. w w w . d i g i e m b e d d e d . c o m A b o u t N S 9 7 5 0 X1_USB X1_USB_OSC NS9750 X2_USB X2_USB_OSC 100 OHM...
Page 41 NS9750 Pinout he NS9750 offers a connection to an external bus expansion module, as well as a glueless connection to SDRAM, PC100 DIMM, flash, EEPROM, and SRAM memories, and an external bus expansion module. It includes a versatile embedded LCD controller, a PCI/CardBus port, a USB port, and four multi-function serial ports.
Page 42: Pinout And Signal Descriptions
If no value appears, that pin is neither a pullup nor pulldown resistor. The type of signal: input, output, or input/output. OD (mA) The output drive of an output buffer. NS9750 uses one of three drivers: More detailed signal descriptions are provided for selected modules. System Memory interface...
Page 43 Pin # Signal Name addr[5] addr[6] addr[7] addr[8] addr[9] addr[10] addr[11] addr[12] addr[13] addr[14] addr[15] addr[16] addr[17] addr[18] addr[19] addr[20] addr[21] addr[22] addr[23] addr[24] addr[25] addr[26] addr[27] clk_en[0] clk_en[1] clk_en[2] Table 3: System Memory interface pinout (mA) Description Address bus signal Address bus signal Address bus signal Address bus signal...
Page 44 P i n o u t a n d s i g n a l d e s c r i p t i o n s Pin # Signal Name clk_en[3] clk_out[0] clk_out[1] clk_out[2] clk_out[3] data[0] data[1] data[2] data[3] data[4] data[5] data[6]...
Page 45 Pin # Signal Name data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[30] data[31] data_mask[0] data_mask[1] data_mask[2] data_mask[3] clk_in[0] clk_in[1] clk_in[2] clk_in[3] byte_lane_sel_n[0] byte_lane_sel_n[1] byte_lane_sel_n[2] byte_lane_sel_n[3] cas_n Table 3: System Memory interface pinout (mA) Description Data bus signal Data bus signal Data bus signal Data bus signal Data bus signal...
Page 46: System Memory Interface Signals
P i n o u t a n d s i g n a l d e s c r i p t i o n s Pin # Signal Name dy_cs_n[0] dy_cs_n[1] dy_cs_n[2] dy_cs_n[3] st_oe_n ras_n dy_pwr_n st_cs_n[0] st_cs_n[1] st_cs_n[2] st_cs_n[3] we_n...
Page 47 As an alternative, you can use an analog switch to connect the clock enables to the SDRAM devices to a pullup resistor until the NS9750 device reset is complete, as indicated by a high level on the reset_done output. See the sample circuit shown in Figure 7, "NS9750 clock enable...
Page 48 P i n o u t a n d s i g n a l d e s c r i p t i o n s Figure 6 shows NS9750 SDRAM clock termination. All series termination resistors must be placed close to driver...
Page 49: Ethernet Interface
NS9750 Figure 7: NS9750 clock enable configuration Ethernet interface Signal name Pin # enet_phy_i nt_n mdio rx_clk rx_dv rx_er rxd[0] Table 5: Ethernet interface pinout 0 = B0 TO A 3.3V NC7SB3157 (mA) RMII crs_dv enet_phy_i nt_n mdio...
Page 50: Clock Generation/System Pins
(mA) Description RMII Receive data bit 1 Receive data bit 1 Receive data bit 2 Pull low external to NS9750 Receive data bit 3 Pull low external to NS9750 Transmit clock Pull low external to NS9750 Transmit enable Transmit enable...
Page 51 Pin # Signal name AD20 bist_en_n AF21 pll_test_n AE21 scan_en_n sys_pll_dvdd sys_pll_dvss sys_pll_avdd sys_pll_avss lcdclk boot_strap[0] boot_strap[1] boot_strap[2] boot_strap[3] boot_strap[4] Table 6: Clock generation and system pin pinout (mA) Description Enable internal BIST operation Enable PLL testing Enable internal scan testing System clock PLL 1.5V digital power System clock PLL digital ground System clock PLL 3.3V analog power...
Page 52: Bist_En_N, Pll_Test_N, And Scan_En_N
P i n o u t a n d s i g n a l d e s c r i p t i o n s bist_en_n, pll_test_n, and scan_en_n Table 7 is a truth/termination table for Normal operation pll_test_n pull up bist_en_n...
Page 53 Pin # Signal name ad[12] ad[13] ad[14] ad[15] ad[16] ad[17] ad[18] ad[19] ad[20] ad[21] ad[22] ad[23] ad[24] AA25 ad[25] AB26 ad[26] AA24 ad[27] AB25 ad[28] AC26 ad[29] AD26 ad[30] AC25 ad[31] cbe_n[0] cbe_n[1] cbe_n[2] AA26 cbe_n[3] devsel_n frame_n Table 8: PCI interface pinout (mA) Description PCI time-multiplexed address/data bus...
Page 54 For PCI host applications, connect to AD11. For PCI device applications, connection is determined by the PCI device number assigned to the NS9750. For CardBus applications, connect to the external pullup resistor. Do not allow input to float in any application.
Page 55 Most of the CardBus signals are the same as the PCI signals. Other CardBus signals are unique and multiplexed with PCI signals for the NS9750. Table 9 shows these unique signals. Figure 8 illustrates how to terminate an unused PCI.
Page 56 Output Input Input Input Description Voltage sense pin. Normally driven low by NS9750, but toggled during the interrogation of the external CardBus device to find voltage requirements. Note: Do not connect directly to the CardBus connector. See the diagram "CardBus system connections to NS9750"...
Page 57 1. Startup code needs to put the PCI bridge into reset. 2. PCI Mode: Boot_strap[1].N3 = default; no pulldown. 3. NS9750 is current PCI bus master. Signals that it can drive should have individual pullups. Figure 8: NS9750 unused PCI termination...
Page 58: Gpio Mux
P i n o u t a n d s i g n a l d e s c r i p t i o n s GPIO MUX The BBus utility contains the control pins for each GPIO MUX bit. Each pin can be selected individually;...
Page 59 Signal Pin # name AE17 gpio[4] AF17 gpio[5] AD16 gpio[6] AE16 gpio[7] AD15 gpio[8] AE15 gpio[9] AF15 gpio[10] AD14 gpio[11] Table 10: GPIO MUX pinout (mA) Description (4 options: 00, 01, 02, 03) Ser port B DTR 1284 busy (peripheral-driven) DMA ch 1 done GPIO 4 Ser port B DSR...
Page 60 P i n o u t a n d s i g n a l d e s c r i p t i o n s Signal Pin # name AE14 gpio[12] AF14 gpio[13] AF13 gpio[14] AE13 gpio[15] AD13 gpio[16] AF12 gpio[17]...
Page 61 Signal Pin # name AC12 gpio[20] AF11 gpio[21] AE11 gpio[22] AD11 gpio[23] AF10 gpio[24] AE10 gpio[25] AD10 gpio[26] gpio[27] Table 10: GPIO MUX pinout (mA) Description (4 options: 00, 01, 02, 03) Ser port C DTR LCD clock Reserved GPIO 20 Ser port C DSR LCD frame pulse-vert Reserved...
Page 62 P i n o u t a n d s i g n a l d e s c r i p t i o n s Signal Pin # name gpio[28] gpio[29] gpio[30] gpio[31] gpio[32] gpio[33] gpio[34] gpio[35] Table 10: GPIO MUX pinout N S 9 7 5 0 H a r d w a r e R e f e r e n c e (mA) Description (4 options: 00, 01, 02, 03)
Page 63 Signal Pin # name gpio[36] gpio[37] gpio[38] gpio[39] gpio[40] gpio[41] gpio[42] gpio[43] Table 10: GPIO MUX pinout (mA) Description (4 options: 00, 01, 02, 03) Reserved 1284 Data 5 (bidirectional) LCD data bit 12 GPIO 36 Reserved 1284 Data 6 (bidirectional) LCD data bit 13 GPIO 37 Reserved...
Page 64 273). Note that the GPIO pins used as bootstrap pins have a defined powerup state that is required for the appropriate NS9750 configuration. If these GPIO pins are also used to control external devices (for example, power switch enable), the powerup state for the external device should be compatible with the boostrap state.
Page 65 See "Example: Implementing gpio[16] and gpio[17]" on page 41 for an illustration. signal GPIO6 or GPIO16 can be used as a code-controlled direction pin for the transceiver. nFault The polarity cannot be altered inside the NS9750; an inverter will be required. Table 10: GPIO MUX pinout Example: Implementing gpio[16] and gpio[17]...
Page 66: Lcd Module Signals
P i n o u t a n d s i g n a l d e s c r i p t i o n s LCD module signals The LCD module signals are multiplexed with GPIO pins. They include seven control signals and up to 24 data signals.
Page 67: Usb Interface
C interface Bits Signal name AC15 iic_scl AF16 iic_sda Table 12: I C interface pinout USB interface Notes: If not using the USB interface, these pins should be pulled down to ground through a 15K ohm resistor. All output drivers for USB meet the standard USB driver specification. Bits Signal name usb_dm...
Page 68 AE19 AC18 TRSTn AF20 AD19 TRST* RTCK JTAG NS9750 Notes out: Boot from flash/ROM/S_CS1n in: Boot from SDRAM/CS0n using SPI_B EEPROM on GPIO pins out: Internal PCI arbiter in: External PCI arbiter bus Debug Load all except JP1/R9, R15, R16; R8 and R12...
Page 69: Reserved
Reserved Pin# AF22 AD21 AE22 Table 15: Reserved pins Description Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly Tie to ground directly...
Page 70: Power Ground
P i n o u t a n d s i g n a l d e s c r i p t i o n s Power ground Pin # J23, L23, K23, U23, T23, V23, D18, D17, AC17, D16, AC16, D11, D10, AC11, AC10, AC9, J4, L4, K4, U4, T4, V4 G23, H23, M23, R23, P23, N23, Y23,...
Page 71 Working with the CPU he NS9750 core is based on the ARM926EJ-S processor. The ARM926EJ-S processor belongs to the ARM9 family of general-purpose microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications in which full memory management, high performance, low die size, and low power are important.
Page 72: About The Processor
A b o u t t h e p r o c e s s o r About the processor The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instructions sets, allowing you to trade off between high performance and high code density. The processor includes features for efficient execution of Java byte codes, providing Java performance similar to JIT but without the associated overhead.
Page 73: Instruction Sets
Figure 10 shows the main blocks in the ARM926EJ-S processor. WDATA RDATA ARM926EJ-S INSTR Figure 10: ARM926EJ-S processor block diagram Instruction sets The processor executes three instruction sets: 32-bit ARM instruction set 16-bit Thumb instruction set 8-bit Java instruction set DEXT Write buffer DROUTE...
Page 74: Arm Instruction Set
I n s t r u c t i o n s e t s ARM instruction set The ARM instruction set allows a program to achieve maximum performance with the minimum number of instructions. The majority of instructions are executed in a single cycle.
Page 75: System Control Processor (Cp15) Registers
System control processor (CP15) registers The system control processor (CP15) registers configure and control most of the options in the ARM926EJ-S processor. Access the CP15 registers using only the MRC and MCR instructions in a privileged mode; the instructions are provided in the explanation of each applicable register.
Page 76: Accessing Cp15 Registers
S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Accessing CP15 registers Use only Figure 11 shows the MRC and MCR instruction bit pattern.
Page 77: Register Summary
Term UNDEFINED SHOULD BE ZERO SHOULD BE ONE SHOULD BE ZERO or PRESERVED Table 17: CP15 terms and abbreviations In all cases, reading from or writing any data values to any CP15 registers, Note: including those fields specified as SHOULD BE ZERO, Register summary CP15 uses 16 registers.
Page 78 S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Register Reads Reserved Data fault status (based on Instruction fault status (based on value)
Page 79: R0: Id Code And Cache Type Status Registers
R0: ID code and cache type status registers Register R0 access the ID register, and cache type register. Reading from R0 returns the device ID, and the cache type, depending on the opcode_2=0 opcode_2=1 field SHOULD BE ZERO instructions you can use to read register R0. Function Read ID code Read cache type...
Page 80 Cache lockdown: Format C (see "R9: Cache Lockdown register" on page 69) S bit Specifies whether the cache is a unified cache (S=0) or separate ICache and DCache (S=1). Will always report separate ICache and DCache for NS9750. Dsize Specifies the size, line length, and associativity of the DCache.
Page 81 Size field 0b0011 0b0100 Note: The NS9750 always reports 4KB for DCache and 8KB for ICache. Assoc Determines the cache associativity in conjunction with the M bit. The M bit is 0 for both DCache and ICache. The assoc field is bits [17:15 for the DCache and bits [5:3] for the ICache.
Page 82: R1: Control Register
S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s R1: Control register Register R1 is the control register for the ARM926EJ-S processor.
Page 83 Bits Name [15] [14] RR bit [13] V bit [12] I bit [11:10] R bit S bit B bit [6:3] C bit A bit Table 22: R1: Control register bit definition W o r k i n g w i t h t h e C P U Function Determines whether the T is set when load instructions change the PC.
Page 84 S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Bits Table 22: R1: Control register bit definition The M, C, I, and RR bits directly affect ICache and DCache behavior, as shown: Cache ICache disabled...
Page 85: R2: Translation Table Base Register
R2: Translation Table Base register Register R2 is the Translation Table Base register (TTBR), for the base address of the first-level translation table. Reading from R2 returns the pointer to the currently active first-level translation table in bits [31:14] and an Writing to R2 updates the pointer to the first-level translation table from the value in bits[31:14] of the written value.
Page 86: R4 Register
S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Each two-bit field defines the access permissions for one of the 16 domains (D15–D0): Use these instructions to access the Domain Access Control register: MRC p15, 0, Rd, c3, c0, 0 ;...
Page 87 Figure 16 shows the format of the Fault Status registers. Table 24 describes the Fault Status register bits. UNP/SBZ Figure 16: Fault Status registers format Bits Description [31:9] UNPREDICTABLE/SHOULD BE ZERO Always reads as zero. Writes are ignored. [7:4] Specifies which of the 16 domains (D15–D0) was being accessed when a data fault occurred.
Page 88: R6: Fault Address Register
S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Priority Source Lowest External abort Table 25: Fault Status register status field encoding R6: Fault Address register...
Page 89 Function Invalidate cache Invalidate single entry using either index or modified virtual address Clean single data entry using either index or modified virtual address Clean and invalidate single data entry using wither index or modified virtual address. Test and clean DCache Test, clean, and invalidate DCache Prefetch ICache line Drain write buffer...
Page 90 S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Function Wait for interrupt Table 26: Cache Operations register function descriptions Function/operation Invalidate ICache and DCache...
Page 91 Figure 17 shows the modified virtual address format for operations. The tag, set, and word fields define the MVA. For all cache operations, the word field Figure 17: R7: MVA format Figure 18 shows the Set/Way format for A and S are the base-two logarithms of the associativity and the number of sets.
Page 92: R8:Tlb Operations Register
S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s found, one of those lines is cleaned. The test and clean DCache instruction also returns the status of the entire DCache in bit 30.
Page 93: R9: Cache Lockdown Register
Operation Invalidate set-associative TLB Invalidate single entry Invalidate set-associative TLB Invalidate single entry Invalidate set-associative TLB Invalidate single entry Table 28: R8: Translation Lookaside Buffer operations The invalidate TLB operations invalidate all the unpreserved entries in the TLB. The invalidate TLB single entry operations invalidate any TLB entry corresponding to the modified virtual address given in preserved state.
Page 94 S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s These registers allow you to control which cache-ways of the four-way cache are used for the allocation on a linefill.
Page 95 This sequence sets the L bit to 1 for way 0 of the ICache. Figure 20 shows the format for the Cache Lockdown register. SBZ/UNP Figure 20: R9: Cache Lockdown register format Table 30 shows the format of the Cache Lockdown register L bits. All cache ways are available for allocation from reset.
Page 96 S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Specific loading of addresses into a cache-way The procedure to lock down code and data into way i of cache, with N ways, using format C, makes it impossible to allocate to any cache way other than the target cache way:...
Page 97: R10: Tlb Lockdown Register
Cache unlock procedure To unlock the locked down portion of the cache, write to Cache Lockdown register (R9) setting L==0 the L bit to 0 for way 0 of the ICache, unlocking way 0: MRC p15, 0, Rn, c9, c0, 1; BIC Rn, Rn, 0x01 ;...
Page 98: R11 And R12 Registers
S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s See "R8:TLB Operations register" on page 68 for a description of the TLB-invalidate operations.
Page 99: R13: Process Id Register
R13: Process ID register The Process ID register accesses the process identifier registers. The register accessed depends on the value on the opcode_2=0 opcode_2=1 Use the Process ID register to determine the process that is currently running. The process identifier is set to 0 at reset. FCSE PID register Addresses issued by the ARM926EJ-S core, in the range 0 to 32 MB, are translated according to the value contained in the FCSE PID register.
Page 100 S y s t e m c o n t r o l p r o c e s s o r ( C P 1 5 ) r e g i s t e r s Figure 22 shows the format of the FCSE PID register. FCSE PID Figure 22: Process ID register format Performing a fast context switch...
Page 101: R14 Register
Figure 23 shows the format of the Context ID register (Rd) transferred during this operation. Figure 23: Context ID register format R14 register Accessing (reading or writing) this register is reserved. R15: Test and debug register Register R15 to provides device-specific test and debug operations in ARM926EJ-S processors.
Page 102: Dsp
D S P The ARM926EJ-S processor core provides enhanced DSP capability. Multiply instructions are processed using a single cycle 32x16 implementation. There are 32x32, 32x16, and 16x16 multiply instructions, or Multiply Accumulate (MAC), and the pipeline allows one multiply to start each cycle. Saturating arithmetic improves efficiency by automatically selecting saturating behavior during execution, and is used to set limits on signal processing calculations to minimize the effect of noise or signal errors.
Page 103 Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions). Hardware page table walks. Invalidate entire TLB using R8: TLB Operations register (see "R8:TLB Operations register" on page 68). Invalidate TLB entry selected by MVA, using R8: TLB Operations register (see "R8:TLB Operations register"...
Page 104 M e m o r y M a n a g e m e n t U n i t ( M M U ) Access is permitted and an off-chip access is not required — the cache services the access. Access is not permitted —...
Page 105: Address Translation
Register R8: TLB Operations register R10: TLB Lockdown register Table 31: MMU program-accessible CP15 registers All CP15 MMU registers, except R8: TLB Operations, contain state that can be read using instructions, and can be written using Status) and R6 (Fault Address) are also written by the MMU during an abort. Writing to R8: TLB Operations causes the MMU to perform a TLB operation, to manipulate TLB entries.
Page 106 M e m o r y M a n a g e m e n t U n i t ( M M U ) The translation process always begins in the same way — with a level-one fetch. A section-mapped access requires only a level-one fetch, but a page-mapped access requires an additional level-two fetch.
Page 107 Figure 25 shows the table walk process. Translation table TTB base Section base Indexed by modified virtual address bits [31:20] 4096 entries Figure 25: Translating page tables Section Indexed by modified virtual address bits [19:0] 1 MB Coarse page Coarse page table table base Indexed by...
Page 108 M e m o r y M a n a g e m e n t U n i t ( M M U ) First-level fetch Bits [31:14] of the TTB register are concatenated with bits [31:20] of the MVA to produce a 30-bit address.
Page 109 Fine page tables, which have 1024 entries and split the 1 MB that the table describes into 1 KB blocks. 20 19 Coarse page table base address Section base address Fine page table base address Figure 27: First-level descriptor Table 32 shows first-level descriptor bit assignments. Bits Section Coarse...
Page 110 M e m o r y M a n a g e m e n t U n i t ( M M U ) Bits Section Coarse [1:0] [1:0] Table 32: Priority encoding of fault status Value Meaning Invalid Coarse page table Section Fine page table...
Page 111 Bits Description [8:5] Specifies one of the 16 possible domains (held in the Domain and Access Control register) that contain the primary access controls. Should be written as 1, for backwards compatibility. [3:2] Indicate if the area of memory mapped by this section is treated as writeback cachable, write-through cachable, noncached buffered, or noncached nonbuffered.
Page 112 M e m o r y M a n a g e m e n t U n i t ( M M U ) Bits [1:0] Table 35: Coarse page table descriptor bits Fine page table descriptor A fine page table descriptor provides the base address of a page table that contains second-level descriptors for large page, small page, or tiny page accesses.
Page 113 Translating section references Figure 31 shows the complete section translation sequence. Translation table base Translation base Translation base Section first-level descriptor 20 19 Section base address Physical address 20 19 Section base address Figure 31: Section translation Second-level descriptor The base address of the page table to be used is determined by the descriptor returned (if any) from a first-level fetch —...
Page 114 M e m o r y M a n a g e m e n t U n i t ( M M U ) Large page base address Small page base address Tiny page base address Figure 32: Second-level descriptor A second-level descriptor defines a tiny, small, or large page descriptor, or is invalid: A large page descriptor provides the base address of a 64 KB block of memory.
Page 115 Bits Large Small Tiny [11:4] [11:4] [5:4] [3:2] [3:2] [3:2] [1:0] [1:0] [1:0] Table 37: Second-level descriptor bits The two least significant bits of the second-level descriptor indicate the descriptor type; see Table 38. Value Meaning Invalid Large page Small page Tiny page Table 38: Interpreting page table entry bits [1:0] Tiny pages do not support subpage permissions and therefore have only...
Page 116 M e m o r y M a n a g e m e n t U n i t ( M M U ) Translation base Translation base Coarse page table base address Coarse page table base address Page base address Page base address Figure 33: Large page translation from a coarse page table Because the upper four bits of the page index and low-order four bits of the coarse...
Page 117 If the large page descriptor is included in a fine page table, the high-order six bits of the page index and low-order six bits of the fine page table overlap. Each fine page table entry for a large page must be duplicated 64 times. Translating small page references Translation table base Translation base...
Page 118 M e m o r y M a n a g e m e n t U n i t ( M M U ) If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap.
Page 119: Mmu Faults And Cpu Aborts
Page translation involves one additional step beyond that of a section translation. The first-level descriptor is the fine page table descriptor; this points to the first- level descriptor. The domain specified in the first-level description and access permissions Note: specified in the first-level description together determine whether the access has permissions to proceed.
Page 120 M e m o r y M a n a g e m e n t U n i t ( M M U ) The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is detected as a result of a memory access, the MMU aborts the access and signals the fault condition to the CPU core.
Page 121 Notes: Alignment faults can write either [3:0] Invalid values can occur in the status bit encoding for domain faults. This happens when the fault is raised before a valid domain field has been read from a page table description. Aborts masked by a higher priority abort can be regenerated by fixing the cause of the higher priority abort, and repeating the access.
Page 122: Domain Access Control
M e m o r y M a n a g e m e n t U n i t ( M M U ) Compatibility issues To enable code to be ported easily to future architectures, it is recommended that no reliance is made on external abort behavior. The Instruction Fault Status register is intended for debugging purposes only.
Page 123: Fault Checking Sequence
Table 42: Interpreting access permission (AP) bits Fault checking sequence The sequence the MMU uses to check for access faults is different for sections and pages. Figure 36 shows the sequence for both types of access. Privileged permissions Read only Read only UNPREDICTABLE Read/write...
Page 124 M e m o r y M a n a g e m e n t U n i t ( M M U ) Section translation Invalid fault Section No access (00) domain Reserved (10) fault Section permission Violation fault Figure 36: Sequence for checking faults The conditions that generate each of the faults are discussed in the following...
Page 125 Alignment faults If alignment fault checking is enabled (the A bit in the R1: Control register is set; see "R1: Control register," beginning on page 58), the MMU generates an alignment fault on any data word access if the address is not word-aligned, or on any halfword access if the address is not halfword-aligned —...
Page 126: External Aborts
M e m o r y M a n a g e m e n t U n i t ( M M U ) Permission faults If the two-bit domain field returns client (01), access permissions are checked as follows: Section: If the level one descriptor defines a section-mapped access, the AP bits of the descriptor define whether the access is allowed, per Table 42:...
Page 127: Enabling The Mmu
Nonbuffered writes Noncached read-lock-write For a read-lock-write externally aborts. A swap to an NCB region is forced to have precisely the same behavior as a swap to an NCNB region. This means that the write part of a swap to an NCB region can be aborted externally.
Page 128: Disabling The Mmu
M e m o r y M a n a g e m e n t U n i t ( M M U ) Disabling the MMU Clear bit 0 (the M bit) in the R1: Control register to disable the MMU. If the MMU is enabled, then disabled, then subsequently re-enabled, the Note: contents of the TLB are preserved.
Page 129: Caches And Write Buffer
times. To guarantee coherency if a level one descriptor is modified in main memory, either an invalidate-TLB or Invalidate-TLB-by-entry operation must be used to remove any cached copies of the level one descriptor. This is required regardless of the type of level one descriptor (section, level two page reference, or fault).
Page 130: Write Buffer
C a c h e s a n d w r i t e b u f f e r The DCache stores the Physical Address Tag (PA tag) corresponding to each DCache entry in the tag RAM for use during cache line write-backs, in addition to the virtual address tag stored in the tag RAM.
Page 131: Enabling The Caches
Enabling the caches On reset, the ICache and DCache entries all are invalidated and the caches disabled. The caches are not accessed for reads or writes. The caches are enabled using the I, C, and M bits from the R1: Control register, and can be enabled independently of one another.
Page 132 C a c h e s a n d w r i t e b u f f e r R1 C bit R1 M bit Table 45: R1: Control register I and M bit settings for DCache Table 46 gives the page table C and B bit settings for the DCache (R1: Control register C bit = M bit = 1), and the associated behavior.
Page 133: Cache Mva And Set/Way Formats
Cache MVA and Set/Way formats This section shows how the MVA and set/way formats of ARM926EJ-S caches map to a generic virtually indexed, virtually addressed cache. Figure 37 shows a generic, virtually indexed, virtually addressed cache. Figure 37: Generic virtually indexed, virtually addressed cache Index Word Byte...
Page 134 C a c h e s a n d w r i t e b u f f e r Figure 38 shows the ARM926EJ-S cache format. Figure 38: ARM926EJ-S cache associativity The following points apply to the ARM926EJ-S cache associativity: The group of tags of the same index defines a set.
Page 135: Noncachable Instruction Fetches
ARM926EJ-S 32 KB 64 KB 128 KB Table 47: Values of S and NSETS Figure 39 shows the set/way/word format for ARM926EJ-S caches. 32-A 31-A Figure 39: ARM926EJ-S cache set/way/word format In this figure: A = log For example, with a 4-way cache A = 2: S = log Noncachable instruction fetches The ARM926EJ-S processor performs speculative noncachable instruction fetches to...
Page 136: Self-Modifying Code
N o n c a c h a b l e i n s t r u c t i o n f e t c h e s Self-modifying code A four-word buffer holds speculatively fetched instructions. Only sequential instructions are fetched speculatively;...
Page 137: Instruction Memory Barrier
Instruction Memory Barrier Whenever code is treated as data — for example, self-modifying code or loading code into memory — a sequence of instructions called an instruction memory barrier (IMB) operation must be used to ensure consistency between the data and instruction streams processed by the ARM926EJ-S processor.
Page 138: Sample Imb Sequences
I n s t r u c t i o n M e m o r y B a r r i e r recommended that either a nonbuffered store ( ) be used to trigger external synchronization. Invalidate the cache. The ICache must be invalidated to remove any stale copies of instructions that are no longer valid.
Page 139: Memory Controller
Memory Controller he Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects to the Advanced High-performance Bus (AHB). The remainder of this chapter refers to this controller as the memory controller. 1 1 5...
Page 140 F e a t u r e s Features The memory controller provides these features: AMBA 32-bit AHB compliancy. Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM. Asynchronous static memory device support including RAM, ROM, and Flash, with and without asynchronous page mode. Can operate with cached processors with copyback caches.
Page 141: System Overview
Little and big endian support. Synchronous static memory devices (synchronous burst mode) are not Note: supported. System overview Figure 40 shows the NS9750 memory controller in a sample system. Bridge/ Arbiter AMBA AHB bus NetSilicon BBus bus Figure 40: NS9750 sample system The largest amount of memory allowed for a single chip select is 256 MB.
Page 142: Low-Power Operation
Low-power operation In many systems, the contents of the memory system have to be maintained during low-power sleep modes. NS9750 provides two features to enable this: Dynamic memory refresh over soft reset A mechanism to place the dynamic memories into self-refresh mode Self-refresh mode can be entered as follows: Set the SREFREQ bit in the Dynamic Memory Control register (see page 208).
Page 143 Chip select 1 memory configuration You can configure the memory width and chip select polarity of static memory chip select 1 by using selected input signals. This allows you to boot from chip select 1. These are the bootstrap signals: Memory width select boot_strap[4:3]: Chip select polarity...
Page 144 F e a t u r e s More boot, initialization, or application code is executed. Example: Boot from flash, SDRAM remapped after boot The system is set up as: Chip select 1 is connected to the boot flash device. Chip select 4 is connected to the SDRAM to be remapped to boot.
Page 145: Static Memory Controller
Static memory controller Table 48 shows configurations for the static memory controller with different types of memory devices. See "Static Memory Configuration 0–3 registers" on page 230 for more information. Device Page mode ROM Extended wait ROM SRAM Page mode SRAM Extended wait SRAM Flash Page mode flash...
Page 146: Write Protection
S t a t i c m e m o r y c o n t r o l l e r Write protection Each static memory chip select can be configured for write-protection. SRAM usually is unprotected and ROM devices must be write-protected (to avoid potential bus conflict when performing a write access to ROM), but the P field in the Static Memory Configuration register (see "Static Memory Configuration 0–3 registers"...
Page 147: Memory Mapped Peripherals
Memory mapped peripherals Some systems use external peripherals that can be accessed using the static memory interface. Because of the way many of these peripherals function, the read and write transfers to them must not be buffered. The buffer must therefore be disabled. Static memory initialization Static memory must be initialized as required after poweron reset programming the relevant registers in the memory controller as well as the...
Page 148 S t a t i c m e m o r y c o n t r o l l e r "Static Memory Page Mode Read Delay 0–3 registers" on page 237 (StaticWaitPage[n]) "Static Memory Turn Round Delay 0–3 registers" on page 239 (StaticWaitTurn[n]) "Static Memory Extended Wait register"...
Page 149 ROM, SRAM, and Flash The memory controller uses the same read timing control for ROM, SRAM, and flash devices. Each read starts with the assertion of the appropriate memory bank chip select signals ( ) and memory address ( STCSOUT_n is determined by the number of wait states programmed for the WAITRD field in the Static Memory Read Delay register.
Page 150 S t a t i c m e m o r y c o n t r o l l e r Cycle T0-T1 T1-T4 T4-T5 T5-T6 Table 50: External memory 0 wait state read Figure 42 shows an external memory read transfer with two wait states ( Seven AHB cycles are required for the transfer, five for the standard read access and an additional two because of the programmed wait states added ( provides the timing parameters.
Page 151 Cycle Description AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory address, chip select, and control signals submitted to static memory. T5-T6 Read wait state 1. T6-T7 Read wait state 2. T7-T8 Read data returned from the static memory.
Page 152 S t a t i c m e m o r y c o n t r o l l e r Timing parameter WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN Table 53: Static memory timing parameters Cycle T0-T1 T1-T4 T4-T5 T5-T6 T6-T7 T7-T8...
Page 153 Table 55 provides the timing parameters. Table 56 describes the transactions for Figure 44. clk_out ADDR DATAIN STCSOUT_n COEOUT_n Figure 44: External memory 2 0 wait state read timing diagram Timing parameter Value WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN Table 55: Static memory timing parameters Cycle Description AHB address provided to memory controller.
Page 154 S t a t i c m e m o r y c o n t r o l l e r Cycle T7-T8 T8-T11 T11-T12 T12-T13 Table 56: External memory 2 0wait state reads Figure 45 shows a burst of zero wait state reads with the length specified. Because the length of the burst is known, the chip select can be held asserted during the whole burst and generate the external transfers before the current AHB transfer has completed.
Page 155 Timing parameter Value WAITWEN WAITTURN Table 57: SRAM timing parameters Cycle Description AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory read 0 address, chip select, and control signals submitted to static memory. T5-T6 Static memory read 1 address, chip select, and control signals submitted to static memory.
Page 156 S t a t i c m e m o r y c o n t r o l l e r clk_out ADDR DATAIN SCTSOUT_n COEOUT_n Figure 46: External memory 2 wait states fixed length burst read timing diagram Timing parameter WAITRD WAITOEN...
Page 157 Cycle Description T7-T8 Read data 0 returned from the static memory. Read data 0 is provided to the AHB. Static memory transfer 1, address, chip select, and control signals submitted to static memory. T8-T9 Read wait state 1. T9-T10 Read wait state 2. T10-T11 Read data 1 returned from the static memory.
Page 158 S t a t i c m e m o r y c o n t r o l l e r clk_out ADDR DATAIN SCTSOUT_n OEOUT_n Figure 47: External memory page mode read transfer timing diagram Timing parameter WAITRD WAITOEN WAITPAGE WAITWR...
Page 159 Cycle Description T8-T9 Read page mode wait state 1. T9-T10 Read data 1 returned from the static memory. Read data 1 is provided to the AHB. Static memory transfer 2, address, chip select, and control signals submitted to static memory. T10-T11 Read page mode wait state 1.
Page 160 S t a t i c m e m o r y c o n t r o l l e r Timing parameters WAITWR WAITWEN WAITTURN Table 63: Static memory timing parameters Cycle T0-T1 T1-T4 T4-T5 T5-T6 T6-T7 T7-T8 T8-T9 Table 64: External memory 32-bit burst read from 8-bit memory Static memory write control...
Page 161 deasserted a cycle before the chip select, at the end of the transfer. lane signal) has the same timing as devices that use the byte lane selects instead of the write enables. SRAM Write timing for SRAM starts with assertion of the appropriate memory bank chip selects ( ) and address signals ( STCSOUT[n]_n...
Page 162 S t a t i c m e m o r y c o n t r o l l e r Timing parameters WAITWEN WAITTURN Table 65: Static memory timing parameters Cycle T0-T1 T1-T4 T4-T5 T5-T6 T6-T7 T7-T8 Table 66: External memory 0 wait state write Figure 50 shows a single external memory write transfer with two wait states ).
Page 163 clk_out ADDR DATAOUT STCSOUT_n WEOUT_n Figure 50: External memory 2 wait state write timing diagram Timing parameter Value WAITRD WAITOEN WAITPAGE WAITWR WAITWEN WAITTURN Table 67: Static memory timing parameters Cycle Description AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports.
Page 164 S t a t i c m e m o r y c o n t r o l l e r Cycle T6-T7 T7-T8 T8-T9 T9-T10 Table 68: External memory 2 wait state write Figure 51 shows a single external memory write transfer with two write enable delay states ( WAITWEN=2 parameters.
Page 165 Cycle Description AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory transfer 0, address, chip select, and control signals submitted to static memory. Write data is read from the AHB memory port. Write enable active.
Page 166 S t a t i c m e m o r y c o n t r o l l e r clk_out ADDR DATAOUT SCTSOUT_n WEOUT_n Figure 52: External memory 2 0 wait writes timing diagram Timing parameter WAITRD WAITOEN WAITPAGE WAITWR...
Page 167 Cycle Description T6-T7 Static memory writes data 0. Write enable taken inactive. Write data 1 is read from AHB memory port. T7-T8 Static memory control signals taken inactive. T8-T9 Memory controller processing. T9-T10 Static memory transfer 1, address, chip select, and control signals submitted to static memory.
Page 168 S t a t i c m e m o r y c o n t r o l l e r clk_out ADDR DATAIN DATAOUT OEOUT STCSOUT_n WEOUT_n DATAEN_n Figure 53: Read followed by write (both 0 wait) with no turnaround Timing parameter WAITRD WAITOEN...
Page 169 Cycle Description T5-T6 Memory controller processing. T6-T7 Memory controller processing. T7-T8 Static memory transfer address, chip select, and control signals submitted to static memory. Write data is read from AHB memory port. Write enable inactive. T8-T9 Write enable taken active. Write data submitted to static memory.
Page 170 S t a t i c m e m o r y c o n t r o l l e r Table 75 provides the timing parameters. Table 76 describes the transactions for Figure 54. clk_out ADDR DATAIN DATAOUT COEOUT_n STCSOUT_n WEOUT_n...
Page 171 Cycle Description T4-T5 Static memory address, chip select, and control signals submitted to static memory. Write data is read from AHB memory port. Write enable inactive. AHB read address provided to memory controller. T5-T6 Write enable taken active. Write data submitted to static memory. T6-T7 Static memory writes the data.
Page 172 S t a t i c m e m o r y c o n t r o l l e r Table 77 provides the timing parameters. Table 78 describes the transactions for Figure 55. clk_out ADDROUT DATAIN DATAOUT OEOUT_n CSTCSOUT_n WEOUT_n...
Page 173: Byte Lane Control
Cycle T4-T5 T5-T6 T6-T7 T7-T8 T8-T9 T9-T10 T10-T11 T11-T12 Table 78: Read followed by a write (all 0 wait state) with two turnaround cycles Byte lane control The memory controller generates the byte lane control signals to these attributes: Little or big endian operation AMBA transfer width, indicated by External memory bank databus width, defined within each control register The decoded...
Page 174: Address Connectivity
S t a t i c m e m o r y c o n t r o l l e r partitioned memory devices" on page 150 and "Memory banks constructed from 8-bit or non-byte-partitioned memory devices" on page 150 explain why different connections, with respect to configurations.
Page 175 Figure 56: Memory banks constructed from 8-bit memory Figure 56 shows 8-bit memory configuring memory banks that are 8-, 16-, and 32-bits wide. In each of these configurations, the enable ( ) inputs of each 8-bit memory. The WE_n controller is not used. For write transfers, the appropriate asserted low, and direct the data to the addressed bytes.
Page 176 S t a t i c m e m o r y c o n t r o l l e r ADDROUT[20:0] STCSOUT_n OEOUT_n WEOUT_n BLSOUT[3]_n BLSOUT[2]_n BLSOUT[1]_n BLSOUT[0]_n DATA[31:0] 32-bit bank consisting of one 32-bit device Figure 58: Memory banks constructed from 32-bit memory Figure 59 shows connections for a typical memory system with different data width memory devices.
Page 177 ADDROUT[20:0] STCSOUT[0]_n OEOUT_n STCSOUT[1]_n WEOUT_n STCSOUT[2]_n BLSOUT[3]_n BLSOUT[2]_n BLSOUT[1]_n BLSOUT[0]_n Figure 59: Typical memory connection diagram (1) ADDROUT[20:0] DATAOUT[31:0] A[20:0] Q[31:0] CE_n OE_n 2Mx32 burst mask ROM ADDROUT[15:0] DATAOUT[31:16] A[15:0] IO[15:0] CE_n OE_n WE_n UB_n LB_n ADDROUT[15:0] DATAOUT[15:0] A[15:0] IO[15:0] CE_n OE_n WE_n...
Page 178: Byte Lane Control And Databus Steering
S t a t i c m e m o r y c o n t r o l l e r Byte lane control and databus steering For little and big endian configurations, address right-justified The tables in this section (Table 79 through Table 125) show the relationship of signals HSIZE[2:0] between the AHB system databus and the external memory databus.
Page 179 Access: Read, little endian, 16-bit external bus Internal transfer width HSIZE HADDR [2:0] [1:0] Word (2 transfers Halfword Halfword Byte Byte Byte Byte Table 80: Little endian read, 16-bit external bus Access: Read, little endian, 32-bit external bus Internal transfer width HSIZE HADDR...
Page 180 S t a t i c m e m o r y c o n t r o l l e r Access: Read, little endian, 32-bit external bus Internal transfer width HSIZE [2:0] Byte Byte Byte Table 81: Little endian read, 32-bit external bus Access: Write, little endian, 8-bit external bus Internal...
Page 181 Access: Write, little endian, 16-bit external bus Internal transfer width HSIZE HADD ADDROUT [2:0] R [1:0] Word (2 transfers Halfword Halfword Byte Byte Byte Byte Table 83: Little endian write, 16-bit external bus Access: Write, little endian, 32-bit external bus Internal transfer width...
Page 182 S t a t i c m e m o r y c o n t r o l l e r Access: Write, little endian, 32-bit external bus Internal transfer width HSIZE [2:0] Byte Byte Table 84: Little endian write, 32-bit external bus Access: Read, big endian, 8-bit external Internal transfer...
Page 183 Access: Read, big endian, 16-bit external Internal transfer width HSIZE HADDR [2:0] [1:0] Word (2 transfers Halfword Halfword Byte Byte Byte Byte Table 86: Big endian read, 16-bit external bus Access: Read, big endian, 32-bit external Internal transfer width HSIZE HADDR [2:0] [2:1]...
Page 184 S t a t i c m e m o r y c o n t r o l l e r Access: Read, big endian, 32-bit external Internal transfer width HSIZE [2:0] Byte Byte Table 87: Big endian read, 32-bit external bus Access: Write, big endian, 8-bit external Internal transfer...
Page 185 Access: Write, big endian, 16-bit external bus Internal transfer width HSIZE HADD ADDROUT [2:0] R [1:0] [1:0] Word (2 transfers Halfword Halfword Byte Byte Byte Byte Table 89: Big endian write, 16-bit external bus Access: Write, big endian, 32-bit external bus Internal transfer width...
Page 186: Dynamic Memory Controller
D y n a m i c m e m o r y c o n t r o l l e r Access: Write, big endian, 32-bit external bus Internal transfer width HSIZE [2:0] Byte Byte Table 90: Big endian write, 32-bit external bus Dynamic memory controller Write protection Each dynamic memory chip select can be configured for write-protection by setting...
Page 187: Address Mapping
Word transfers are the widest transfers supported by the memory controller. Any access tried with a size larger than a word generates an error response. Address mapping This section provides tables that show how AHB address bus addresses map to the external dynamic memory address and bus widths.
Page 188 D y n a m i c m e m o r y c o n t r o l l e r devices. The row-bank-column address mapping scheme allows memory accesses to be performed efficiently to nearby memory regions. 32-bit wide databus address mappings (BRC) (see "32-bit wide databus –...
Page 189 Output address Memory device connections ADDROUT Table 91: Address mapping for 16M SDRAM (1Mx16, RBC) Table 92 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 14 used as bank select). Output address Memory device connections ADDROUT...
Page 190 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 92: Address mapping for 16M SDRAM (2Mx8, RBC) Table 93 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (2Mx32, pins 13 and 14 used as bank selects).
Page 191 Table 94 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections ADDROUT 10/AP Table 94: Address mapping for 64M SDRAM (4Mx16, RBC) M e m o r y C o n t r o l l e r AHB address to row AHB address to...
Page 192 D y n a m i c m e m o r y c o n t r o l l e r Table 95 shows the outputs from the memory controller and the corresponding inputs to the 64 M SDRAM (8Mx8, pins 13 and 14 used as bank selects). Output address ADDROUT Table 95: Address mapping for 64M SDRAM (8Mx8, RBC)
Page 193 Output address Memory device connections ADDROUT 10/AP Table 96: Address mapping for 128M SDRAM (4Mx32, RBC) Table 97 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 194 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 97: Address mapping for 128 SDRAM (8Mx16, RBC) Table 98 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (16Mx8, pins 13 and 14 used as bank selects).
Page 195 Output address Memory device connections ADDROUT Table 98: Address mapping for 128 SDRAM (16Mx8, RBC) Table 99 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (8Mx32, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 196 D y n a m i c m e m o r y c o n t r o l l e r Table 100 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects). Output address ADDROUT Table 100: Address mapping for 256M SDRAM (16Mx16, RBC)
Page 197 Output address Memory device connections ADDROUT 10/AP Table 101: Address mapping for 256M SDRAM (32Mx8, RBC) Table 102 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 198 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 102: Address mapping for 512M SDRAM (32Mx16, RBC) Table 103 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
Page 199 Output address Memory device connections ADDROUT Table 103: Address mapping for 512M SDRAM (64Mx8, RBC) 32-bit wide databus address mappings (BRC) Table 104 through Table 116 show 32-bit wide databus address mappings for several SDRAM (BRC) devices. Table 104 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (1x16, pin 14 used as bank select).
Page 200 D y n a m i c m e m o r y c o n t r o l l e r Table 105 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 13 used as bank select). Output address ADDROUT Table 105: Address mapping for 16M SDRAM (2Mx8, BRC)
Page 201 Output address Memory device connections ADDROUT 10/AP Table 106: Address mapping for 64M SDRAM (2Mx32, BRC) Table 107 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 202 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 107: Address mapping for 64M SDRAM (4Mx16, BRC) Table 108 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
Page 203 Output address Memory device connections ADDROUT Table 108: Address mapping for 64M SDRAM (8Mx8, BRC) Table 109 shows the outputs from the memory controller and the corresponding inputs to the 128M SDSRAM (4Mx32, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 204 D y n a m i c m e m o r y c o n t r o l l e r Table 110 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (8Mx16, pins 13 and 14 used as bank selects). Output address ADDROUT Table 110: Address mapping for 128M SDRAM (8Mx16, BRC)
Page 205 Output address Memory device connections ADDROUT 10/AP Table 111: Address mapping for 128M SDRAM (16Mx8, BRC) Table 112 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (8Mx32, pins 13 and 14 used as bank selects. Output address Memory device connections...
Page 206 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 112: Address mapping for 256M SDRAM (8Mx32, BRC) Table 113 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Page 207 Output address Memory device connections ADDROUT Table 113: Address mapping for 256M SDRAM (16Mx16, BRC) Table 114 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 208 D y n a m i c m e m o r y c o n t r o l l e r Table 115 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects). Output address ADDROUT Table 115: Address mapping for 512M SDRAM (32Mx16, BRC)
Page 209 Output address Memory device connections ADDROUT 10/AP Table 116: Address mapping for 512M SDRAM (64x8, BRC) 16-bit wide databus address mappings, SDRAM (RBC) Table 117 through Table 126 show 16-bit wide databus address mappings for SDRAM (RBC) devices. Table 117 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (1Mx16, pin 14 used as bank select).
Page 210 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 117: Address mapping for 16M SDRAM (1Mx16, RBC) Table 118 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 13 used as bank select).
Page 211 Output address Memory device connections ADDROUT Table 118: Address mapping for 16M SDRAM (2Mx8, RBC) Table 119 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 212 D y n a m i c m e m o r y c o n t r o l l e r Table 120 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects). Output address ADDROUT Table 120: Address mapping for 64M SDRAM (8Mx8, RBC)
Page 213 Output address Memory device connections ADDROUT 10/AP Table 121: Address mapping for 128M SDRAM (8Mx16, RBC) Table 122 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (16Mx8, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 214 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 122: Address mapping for 128M SDRAM (16Mx8, RBC) Table 123 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Page 215 Output address Memory device connections ADDROUT Table 123: Address mapping for 256M SDRAM (16Mx16, RBC) Table 124 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 216 D y n a m i c m e m o r y c o n t r o l l e r Table 125 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects). Output address ADDROUT Table 125: Address mapping for 512M SDRAM (32Mx16, RBC)
Page 217 Table 126 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects). Output address Memory device connections ADDROUT 10/AP Table 126: Address mapping for 512M SDRAM (64Mx8, RBC) 16-bit wide databus address mappings (BRC) Table 127 through Table 136 show 16-bit wide databus address mappings for SDRAM (BRC) devices.
Page 218 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 127: Address mapping for 16M SDRAM (1Mx16, BRC) Table 128 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 14 used as a bank select).
Page 219 Output address Memory device connections ADDROUT Table 128: Address mapping for 16M SDRAM (2Mx8, BRC) Table 129 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 220 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 129: Address mapping for 64M SDRAM (4Mx16, BRC) Table 130 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx*, pins 13 and 14 used as bank selects).
Page 221 Table 131 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (8Mx16, pins 13 and 14 used as bank selects). Output address Memory device connections ADDROUT 10/AP Table 131: Address mapping for 128M SDRAM (8Mx16, BRC) Table 132 shows the outputs from the memory controller and the corresponding inputs to the 128 SDRAM (16Mx8, pins 13 and 14 used as bank selects).
Page 222 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 132: Address mapping for 128M SDRAM (16Mx8, BRC) Table 133 shows the outputs for the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Page 223 Output address Memory device connections ADDROUT Table 133: Address mapping for 256M SDRAM (16Mx16, BRC) Table 134 shows the outputs for the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects). Output address Memory device connections...
Page 224 D y n a m i c m e m o r y c o n t r o l l e r Output address ADDROUT Table 134: Address mapping for 256M SDRAM (32Mx8, BRC) Table 135 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects).
Page 225 Table 136 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects). Output address Memory device connections ADDROUT 10/AP Table 136: Address mapping for 512M SDRAM (64Mx8, BRC) M e m o r y C o n t r o l l e r AHB address to row AHB address to...
Page 226: Registers
R e g i s t e r s Registers The external memory is accessed using the AHB memory interface ports. Addresses are not fixed, but are determined by the AHB decoder and can be different for any particular system implementation. Transfers to the external memory controller memories are selected by the AHB port number and [7:0] indicates the chip select to be accessed.) Register map...
Page 227 Address Register A070 0048 DynamictRC A070 004C DynamictRFC A070 0050 DynamictXSR A070 0054 DynamictRRD A070 0058 DynamictMRD A070 0080 StaticExtendedWait A070 0100 DynamicConfig0 A070 0104 DynamicRasCas0 A070 0120 DynamicConfig1 A070 0124 DynamicRasCas1 A070 0140 DynamicConfig2 A070 0144 DynamicRasCas2 A070 0160 DynamicConfig3 A070 0164 DynamicRasCas3...
Page 228: Reset Values
R e g i s t e r s Address A070 022C A070 0230 A070 0234 A070 0238 A070 0240 A070 0244 A070 0248 A070 024C A070 0250 A070 0254 A070 0258 A070 0260 A070 0264 A070 0268 A070 026C A070 0270 A070 0274 A070 0278...
Page 229: Control Register
Control register Address: A070 0000 The Control register controls the memory controller operation. The control bits can be changed during normal operation. Register bit assignment Bits Access D31:03 Table 138: Control register Reserved Reserved Mnemonic Description Reserved N/A (do not modify) Low-power mode Normal mode (reset value on Low-power mode...
Page 230 R e g i s t e r s Bits Access Table 138: Control register 2 0 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Description ADDM...
Page 231: Status Register
Status register Address: A070 0004 The Status register provides memory controller status information. Register bit assignment Bits Access D31:03 Table 139: Status register Configuration register Address: A070 0008 Reserved Reserved Mnemonic Description Reserved N/A (do not modify) Self-refresh acknowledge (SREFACK) Normal mode Self refresh mode (reset value on Indicates the memory controller operating mode.
Page 232: Dynamic Memory Control Register
R e g i s t e r s The Configuration register configures memory controller operation. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Page 233 The Dynamic Memory Control register controls dynamic memory operation. The control bits can be changed during normal operation. Rsvd Reserved used Register bit assignment Bits Access Mnemonic D31:15 Reserved Not used D12:09 Reserved D08:07 SDRAMInit Reserved Not used D04:03 Reserved Table 141: Dynamic Memory Control register Reserved SDRAMInit...
Page 234: Dynamic Memory Refresh Timer Register
R e g i s t e r s Bits Access Table 141: Dynamic Memory Control register Dynamic Memory Refresh Timer register Address: A070 0024 The Dynamic Memory Refresh Timer register configures dynamic memory operation. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions.
Page 235 Reserved Register bit assignment Bits Access Mnemonic D31:11 Reserved D10:0 REFRESH Table 142: Dynamic Memory Refresh Timer register Examples Generic formula: DynamicRefresh = (((t For 4k rows: μ Refresh period = 64 Speed grade = 200 MHz Calculation = ((64e / 4096) * 200e For 8k rows: μ...
Page 236: Dynamic Memory Read Configuration Register
R e g i s t e r s Dynamic Memory Read Configuration register Address: A070 0028 The Dynamic Memory Read Configuration register allows you to configure the dynamic memory read strategy. Modify this register only during system initialization. The Dynamic Memory Read Configuration register is used for all four Note: dynamic memory chip selects.
Page 237: Dynamic Memory Precharge Command Period Register
Dynamic Memory Precharge Command Period register Address: A070 0030 The Dynamic Memory Precharge Command Period register allows you to program the precharge command period, t This value normally is found in SDRAM datasheets as t The Dynamic Memory Precharge Command Period register is used for all Note: four dynamic memory chip selects.
Page 238: Dynamic Memory Active To Precharge Command Period Register
R e g i s t e r s Dynamic Memory Active to Precharge Command Period register Address: A070 0034 The Dynamic Memory Active to Precharge Command Period register allows you to program the active to precharge command period, t register be modified during system initialization, or when there are no current or outstanding transactions.
Page 239: Dynamic Memory Self-Refresh Exit Time Register
Dynamic Memory Self-refresh Exit Time register Address: A070 0038 The Dynamic Memory Self-refresh Exit Time register allows you to program the self- refresh exit time, t system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM data sheets as t The Dynamic Memory Self-refresh Exit Time register is used for all four Note:...
Page 240: Dynamic Memory Last Data Out To Active Time Register
R e g i s t e r s Dynamic Memory Last Data Out to Active Time register Address: A070 003C The Dynamic Memory Last Data Out to Active Time register allows you to program the last-data-out to active command time, t modified during system initialization, or when there are no current or outstanding transactions.
Page 241: Dynamic Memory Data-In To Active Command Time Register
Dynamic Memory Data-in to Active Command Time register Address: A070 0040 The Dynamic Memory Data-in to Active Command Time register allows you to program the data-in to active command time, t modified during system initialization, or when there are no current or outstanding transactions.
Page 242: Dynamic Memory Write Recovery Time Register
R e g i s t e r s Dynamic Memory Write Recovery Time register Address: A070 0044 The Dynamic Memory Write Recovery Time register allows you to program the write recovery time, t initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Page 243: Dynamic Memory Active To Active Command Period Register
Dynamic Memory Active to Active Command Period register Address: A070 0048 The Dynamic Memory Active to Active Command Period register allows you to program the active to active command period, t register be modified during system initialization, or when there are no current or outstanding transactions.
Page 244: Dynamic Memory Auto Refresh Period Register
R e g i s t e r s Dynamic Memory Auto Refresh Period register Address: A070 004C The Dynamic Memory Auto Refresh Period register allows you to program the auto- refresh period and the auto-refresh to active command period, t recommended that this register be modified during initialization, or when there are no current or outstanding transactions.
Page 245: Dynamic Memory Exit Self-Refresh Register
Dynamic Memory Exit Self-refresh register Address: A070 0050 The Dynamic memory Exit Self-refresh register allows you to program the exit self- refresh to active command time, t modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Page 246: Dynamic Memory Active Bank A To Active Bank B Time Register
R e g i s t e r s Dynamic Memory Active Bank A to Active Bank B Time register Address: A070 0054 The Dynamic Memory Active Bank A to Active Bank B Time register allows you to program the active bank A to active bank B latency, t register be modified during system initialization, or when there are no current or outstanding transactions.
Page 247: Dynamic Memory Load Mode Register To Active Command Time Register
Dynamic Memory Load Mode register to Active Command Time register Address: A070 0058 The Dynamic Memory Load Mode register to Active Command Time register allows you to program the Load Mode register to active command time, t that this register be modified during system initialization, or when there are no current or outstanding transactions.
Page 248: Static Memory Extended Wait Register
R e g i s t e r s Static Memory Extended Wait register Address: A070 0080 The Static Memory Extended Wait register times long static memory read and write transfers (which are longer than can be supported by the Static Memory Read Delay registers (see page 236) or the Static Memory Write Delay registers (see page 238)) when the EW (extended wait) bit in the related Static Memory Configuration register (see page 230) is enabled.
Page 249: Dynamic Memory Configuration 0-3 Registers
Example Static memory read/write time = 16 us CLK frequency = 50 MHz This value must be programmed into the Static Memory Extended Wait register: (16 x 10 x 50 x 10 Dynamic Memory Configuration 0–3 registers Address: A070 0100 / 0120 / 0140 / 0160 The Dynamic Memory Configuration 0–3 registers allow you to program the configuration information for the relevant dynamic memory chip select.
Page 250 R e g i s t e r s Bits Access D12:07 D06:05 D04:03 D02:00 Table 156: Dynamic Memory Configuration 0–3 registers Table 157 shows address mapping for the Dynamic Memory Configuration 0-3 registers. Address mappings that are not shown in the table are reserved. [14] [12] 16-bit external bus high-performance address mapping (row, bank column)
Page 251 [14] [12] [11:9] [8:7] 16-bit external bus low-power SDRAM address mapping (bank, row, column) 32-bit extended bus high-performance address mapping (row, bank, column) Table 157: Address mapping Description 256 Mb (32Mx8), 4 banks, row length=13, column length=10 256 Mb (16Mx16), 4 banks, row length=13, column length=9 512 Mb (64Mx8), 4 banks, row length=13, column length=11 512 Mb (32Mx16), 4 banks, row length=13, column length=10 16 Mb (2Mx8), 2 banks, row length=11, column length=9...
Page 252 R e g i s t e r s [14] [12] 32-bit extended bus low-power SDRAM address mapping (bank, row, column) Table 157: Address mapping A chip select can be connected to a single memory device; in this situation, the chip select data bus width is the same as the device width.
Page 253: Dynamic Memory Ras And Cas Delay 0-3 Registers
Dynamic Memory RAS and CAS Delay 0–3 registers Address: A070 0104 / 0124 / 0144 / 0164 The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS and CAS latencies for the relevant dynamic memory. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
Page 254: Static Memory Configuration 0-3 Registers
R e g i s t e r s Static Memory Configuration 0–3 registers Address: A070 0200 / 0220 / 0240 / 0260 The Static Memory Configuration 0–3 registers configure the static memory configuration. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
Page 255 Bits Access Mnemonic Table 159: Static Memory Configuration 0–3 registers Description Extended wait Extended wait disabled (reset value on Extended wait enabled Extended wait uses the Static Extended Wait register (see page 224) to time both the read and write transfers, rather than the Static Memory Read Delay 0–3 registers (see page 236) and Static Memory Write Delay 0–3 registers (see page 238).
Page 256 R e g i s t e r s Bits Access D05:04 Table 159: Static Memory Configuration 0–3 registers 2 3 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Description Byte lane state...
Page 257 Bits Access Mnemonic Reserved D01:00 Table 159: Static Memory Configuration 0–3 registers Synchronous burst mode memory devices are not supported. Note: Description Page mode Disabled (reset on reset_n Async page mode enabled (page length four) In page mode, the memory controller can burst up to four external accesses.
Page 258: Static Memory Write Enable Delay 0-3 Registers
R e g i s t e r s Static Memory Write Enable Delay 0–3 registers Address: A070 0204 / 0224 / 0244 / 0264 The Static Memory Write Enable Delay 0–3 registers allow you to program the delay from the chip select to the write enable assertion. The Static Memory Write Enable Delay register is used in conjunction with the Static Memory Write Delay registers, to control the width of the write enable signals.
Page 259: Static Memory Output Enable Delay 0-3 Registers
Static Memory Output Enable Delay 0–3 registers Address: A070 0208 / 0228 / 0248 / 0268 The Static Memory Output Enable Delay 0–3 registers allow you to program the delay from the chip select or address change, whichever is later, to the output enable assertion.
Page 260: Static Memory Read Delay 0-3 Registers
R e g i s t e r s Static Memory Read Delay 0–3 registers Address: A070 020C / 022C / 024C / 026C The Static Memory Read Delay 0–3 registers allow you to program the delay from the chip select to the read access. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
Page 261: Static Memory Page Mode Read Delay 0-3 Registers
Static Memory Page Mode Read Delay 0–3 registers Address: A070 0210 / 0230 / 0250 / 0270 The Static Memory Page Mode Read Delay 0–3 registers allow you to program the delay for asynchronous page mode sequential accesses. These registers control the overall period for the read cycle.
Page 262: Static Memory Write Delay 0-3 Registers
R e g i s t e r s Static Memory Write Delay 0–3 registers Address: A070 0214 / 0234 / 0254 / 0274 The Static Memory Write Delay 0–3 registers allow you to program the delay from the chip select to the write access. These registers control the overall period for the write cycle.
Page 263: Static Memory Turn Round Delay 0-3 Registers
Static Memory Turn Round Delay 0–3 registers Address: A070 0218 / 0238 / 0258 / 0278 The Static Memory Turn Round Delay 0–3 registers allow you to program the number of bus turnaround cycles. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
Page 264 R e g i s t e r s 2 4 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 265 M e m o r y C o n t r o l l e r 2 4 1 w w w . d i g i e m b e d d e d . c o m...
Page 266 R e g i s t e r s 2 4 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 267 M e m o r y C o n t r o l l e r 2 4 3 w w w . d i g i e m b e d d e d . c o m...
Page 268 R e g i s t e r s 2 4 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 269 M e m o r y C o n t r o l l e r 2 4 5 w w w . d i g i e m b e d d e d . c o m...
Page 270 R e g i s t e r s 2 4 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 271 M e m o r y C o n t r o l l e r 2 4 7 w w w . d i g i e m b e d d e d . c o m...
Page 272 R e g i s t e r s 2 4 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 273 M e m o r y C o n t r o l l e r 2 4 9 w w w . d i g i e m b e d d e d . c o m...
Page 274 R e g i s t e r s 2 5 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 275 M e m o r y C o n t r o l l e r 2 5 1 w w w . d i g i e m b e d d e d . c o m...
Page 277: System Control Module
System Control Module he System Control Module configures and oversees system operations for the NS9750, and defines both the NS9750 AHB arbiter system and system memory address space. 2 5 3...
Page 278: System Control Module Features
S y s t e m C o n t r o l M o d u l e f e a t u r e s System Control Module features The System Control Module uses the following to configure and maintain NS9750 system operations:...
Page 279: Arbiter Configuration Examples
Ethernet Bbus Figure 60: NS9750 bus architecture The NS9750 high-speed bus contains two arbiters: one for the ARM926 (CPU) and one for the main bus. CPU arbiter. Splits the bandwidth 50–50 between the data and instruction interfaces. If the CPU access is to external memory, no further arbitration is necessary;...
Page 280 S y s t e m b u s a r b i t e r Main arbiter. Contains a 16-entry Bus Request Configuration (BRC) register. Each BRC entry represents a bus request and grant channel. Each request/ grant channel can be assigned to only one bus master at a time. Each bus master can be connected to multiple request/grant channels simultaneously, however, depending on the bus bandwidth requirement of that master.
Page 281: Address Decoding
Ownership Ownership of the data bus is delayed from ownership of the address/control bus. When indicates that a transfer is complete, the master that owns the address/ hready control bus can use the data bus — and continues to own that data bus — until the transaction completes.
Page 282 S y s t e m b u s a r b i t e r SPLIT transfers A SPLIT transfer occurs when a slave is not ready to perform the transfer. The slave splits, or masks, its master, taking away the master’s bus ownership and allowing other masters to perform transactions until the slave has the appropriate resources to perform its master’s transaction.
Page 283 Example 1 Since the 20 Mbyte per master guarantee meets the requirements of all masters, the AHB arbiter will be programmed as follows: BRC0[31:24] = 8’b1_0_00_0000 BRC0[23:16] = 8’b1_0_00_0001 BRC0[15:8] = 8’b1_0_00_0000 BRC0[7:0] = 8’b1_0_00_0010 BRC1[31:24] = 8’b1_0_00_0000 BRC1[23:16] = 8’b1_0_00_0100 BRC1[15:8] = 8’b1_0_00_0000 BRC1[7:0]...
Page 284 S y s t e m b u s a r b i t e r The available bandwidth per master is calculated using this formula: Bandwidth per master: = [(100MHz/2) / (16 clock cycles per access x 6 masters)] x 32 bytes = 16.667 Mbytes/master If the LCD is configured for two arbiter channel slots, then, there are 33.334 Mbytes available, which is greater than the 25 Mbytes required.
Page 285: Address Decoding
Address decoding A central address decoder provides a select signal — Table 166 shows how the system memory address is set up to allow access to the internal and external resources on the system bus. Note that the external memory chip select ranges can be reset after powerup.
Page 286 1 MB Reserved 1 MB Ethernet Communication Module 1 MB Memory controller 1 MB LCD controller 1 MB System Control Module 1526 Reserved assignments for NS9750. hmaster[3:0] hmaster[3:0] assignment 0000 0001 0010 0011 0100 0101 0110 is active high. HPROT[1]...
Page 287: Programmable Timers
Programmable timers NS9750 provides 18 programmable timers: Software watchdog timer Bus monitor timer 16 general purpose timers Software watchdog timer The software watchdog timer, set to specific time intervals, handles gross system misbehaviors. The watchdog timer can be set to timeout in longer ranges of time intervals, typically in seconds.
Page 288: Interrupt Controller
P r o g r a m m a b l e t i m e r s in the appropriate Timer Control register (see "Timer 0–15 Control registers" on page 301). With a 16-bit counter and a 16-bit prescaler, each GPTC can measure external event length up to minutes in range, and can be individually enabled or disabled.
Page 289 This command file initializes the debugger local variables that are used by the user defined On-Stop and Idle-Mode command descriptors. NOTE: DO NOT CHANGE THIS FILE. This file configures the resources needed to use this feature. To specify an On-Stop or Idle-Mode command for your target, add an EW command to your board init file using the syntax shown below to define the sequence of operations, enable or disable them, and set the Idle-Mode timer...
Page 290 P r o g r a m m a b l e t i m e r s Examples: ew MAJIC_ON_STOP_CMD = 1, @$ucd_rd8, FFF00003 Defines an On-Stop command that reads the byte at 0xFFF00003 upon stopping. ew MAJIC_ON_STOP_CMD = 1, @$ucd_rmw16, 80000000, C00, F00 Defines an On-Stop command that reads a 16-bit value from 80000000, masks off bits 11..8, sets those bits to 1100, and writes the result back to 80000000.
Page 291: Interrupt Controller
FIQ has a higher priority than IRQ. FIQ interrupts Most sources of interrupts on NS9750 are from the IRQ line. There is only one FIQ source for timing-critical applications. The FIQ interrupt generally is reserved for timing-critical applications for these reasons: The interrupt service routine is executed directly without determining the source of the interrupt.
Page 292 I n t e r r u p t c o n t r o l l e r Interrupt Source 0 Interrupt Source 1 Interrupt Source 31 Invert Interrupt Source ID Reg 0 Enable Interrupt Source 0 Interrupt Source 1 Interrupt Source 31 Invert Interrupt Source ID Reg 1...
Page 293 The NS9750 interrupt sources are assigned as shown: Interrupt ID Interrupt source Watchdog Timer AHB Bus Error BBus Aggregate Interrupt Reserved Ethernet Module Receive Interrupt Ethernet Module Transmit Interrupt Ethernet Phy Interrupt LCD Module interrupt PCI Bridge Module Interrupt PCI Arbiter Module Interrupt...
Page 294: Vectored Interrupt Controller (Vic) Flow
I n t e r r u p t c o n t r o l l e r Interrupt ID Vectored interrupt controller (VIC) flow A vectored interrupt controller allows a reasonable interrupt latency for IRQ-line interrupts. When an interrupt occurs, the CPU processor determines whether the interrupt is from a FIQ or IRQ line.
Page 295: System Attributes
(see page 300). The PLL settings then are written to the PLL, and the system is reset. The PLL can be configured at powerup by placing pulldowns on the external memory address pins. NS9750 provides internal pullups to produce a default configuration; see "Bootstrap initialization" on page 272 for information about the powerup configuration.
Page 296: System Configuration Registers
S y s t e m a t t r i b u t e s Figure 62 shows how the PLL clock is used to provide the NS9750 system clocks. x1_sys_osc x2_sys_osc 20MHz - 40MHz Note, to use an external...
Page 297 Table 168 indicates how each bit is used to configure the powerup settings, where 1 indicates the internal pullup resistor and 0 indicates an external pulldown resistor. Table 169 shows multiplier values. PLL ND[4:0] Pin name Configuration bits rtck PCI arbiter configuration External PCI arbiter Internal PCI arbiter boot_strap[0]...
Page 298 S y s t e m a t t r i b u t e s Pin name reset_done gpio[19] gpio[17], gpio[12], gpio[10], gpio[8], gpio[4] gpio[2], gpio[0] Table 168: Configuration pins — Bootstrap initialization Register configuration: gpio 17, 12, 10, 8, 4 11010 00100 11000...
Page 299 Register configuration: gpio 17, 12, 10, 8, 4 10001 10110 10111 10100 10101 01010 01011 01000 01001 01110 01111 01100 01101 00010 00011 00000 00001 00110 00111 00100 00101 Table 169: PLL ND[4:0] multiplier values S y s t e m C o n t r o l M o d u l e Multiplier w w w .
Page 300: System Configuration Registers
S y s t e m c o n f i g u r a t i o n r e g i s t e r s There are 32 additional GPIO pins that are used to create a general purpose, user- defined ID register (see "Gen ID register"...
Page 301 Offset [31:24] A090 0048 Timer 1 Reload Count register A090 004C Timer 2 Reload Count register A090 0050 Timer 3 Reload Count register A090 0054 Timer 4 Reload Count register A090 0058 Timer 5 Reload Count register A090 005C Timer 6 Reload Count register A090 0060 Timer 7 Reload Count register A090 0064...
Page 302 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Offset A090 00B4 A090 00B8 A090 00BC A090 00C0 A090 00C4 A090 00C8 A090 00CC A090 00D0 A090 00D4...
Page 303 Offset [31:24] A090 0120 Interrupt Vector Address Register Level 23 A090 0124 Interrupt Vector Address Register Level 24 A090 0128 Interrupt Vector Address Register Level 25 A090 012C Interrupt Vector Address Register Level 26 A090 0130 Interrupt Vector Address Register Level 27 A090 0134 Interrupt Vector Address Register Level 28 A090 0138...
Page 304 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Offset A090 018C A090 0190 A090 0194 A090 0198 A090 019C A090 01A0 A090 01A4 A090 01A8 A090 01AC...
Page 305 Offset [31:24] A090 01F8 System Memory Chip Select 1 Static Memory Base A090 01FC System Memory Chip Select 1 Static Memory Mask A090 0200 System Memory Chip Select 2 Static Memory Base A090 0204 System Memory Chip Select 2 Static Memory Mask A090 0208 System Memory Chip Select 3 Static Memory Base A090 020C...
Page 306: Ahb Arbiter Gen Configuration Register
S y s t e m c o n f i g u r a t i o n r e g i s t e r s AHB Arbiter Gen Configuration register Address: A090 0000 The AHB Arbiter Gen Configuration register contains miscellaneous control settings for the AHB bus arbiter.
Page 307: Brc0, Brc1, Brc2, And Brc3 Registers
BRC0, BRC1, BRC2, and BRC3 registers Address: A090 0004 / 0008 / 000C / 0010 The BRC[0:3] registers control the AHB arbiter bandwidth allocation scheme. Table 172 shows how the channels are assigned in the four registers. Table 173 shows the bit definition, or format, for each channel, using data bits [07:00] as the example.
Page 308: Timer 0–15 Reload Count Registers
S y s t e m c o n f i g u r a t i o n r e g i s t e r s Bits Access D05:04 D03:00 Table 173: BRC0, BRC1, BRC2, BRC3 register Timer 0–15 Reload Count registers Address: A090 0044 (Timer 0) / 0048 / 004C / 0050 / 0054 / 0058 / 005C / 0060 / 0064 / 0068 / 006C / 0070 / 0074 / 0078 / 007C / 0080 (Timer 15) The Timer Reload registers hold the up/down reload value.
Page 309: Timer 0–15 Read Register
Timer 0–15 Read register Address: A090 0084 / 0088 / 008C / 0090 / 0094 / 0098 / 009C / 00A0 / 00A4 / 00A8 / 00AC / 00B0 / 00B4 / 00B8 / 00BC / 00C0 The Timer Read registers read the current state of each Timer register. Register bit assignment Bits Access...
Page 310: Int (Interrupt) Config (Configuration) Registers (0–31)
S y s t e m c o n f i g u r a t i o n r e g i s t e r s Register bit assignment Bits Access D31:00 Table 176: Interrupt vector address register Int (Interrupt) Config (Configuration) registers (0–31) Address: A090 0144 / 0148 / 014C / 0150 / 0154 / 0158 / 015C / 0160 Each Int Config register is 8 bits in length, and programs each interrupt configuration...
Page 311: Register Bit Assignment
Int Config registers 0, 4, 8, 12, 16, 20, 24, 28 Int Config registers 2, 6, 10, 14, 18, 22, 26, 30 Register bit assignment BIts Access Mnemonic D04:00 Table 178: Int Config register Int Config registers 1, 5, 9, 13, 17, Int Config registers 3, 7, 11, 15, 19, 23, 27, 31 Reset Definition...
Page 312: Israddr Register
S y s t e m c o n f i g u r a t i o n r e g i s t e r s ISRADDR register Address: A090 0164 The ISRADDR register provides the current ISRADDR value. The Interrupt Vector Address register for the FIQ interrupt must be assigned a unique value.
Page 313: Interrupt Status Active
Interrupt Status Active Address: A090 0168 The Interrupt Status Active register shows the current interrupt request. Register bit assignment Bits Access D31:00 Table 180: Interrupt Status Active register Interrupt status active (ISA) Interrupt status active (ISA) Mnemonic Reset Description Interrupt status active Provides the status of all active, enabled interrupt request levels, where bit 0 is for the interrupt assigned to level 0, bit 1 is for the interrupt assigned to level 1, and so on...
Page 314 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Interrupt Status Raw Address: A090 016C The Interrupt Status Raw register shows all current interrupt requests. Register bit assignment Bits Access...
Page 315 Timer Interrupt Status register Address: A090 0170 The Timer Interrupt Status register shows all current timer interrupt requests. Register bit assignment Bits Access D31:16 D15:00 Table 182: Timer Interrupt Status register Software Watchdog Configuration register Address: A090 0174 The Software Watchdog Configuration register configures the software watchdog timer operation.
Page 316 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Register bit assignment Bits Access D31:08 D02:00 Table 183: Software Watchdog Configuration register 2 9 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 317 Software Watchdog Timer register Address: A090 0178 The Software Watchdog Timer register services the watchdog timer. Register bit assignment Bits Access D31:00 Table 184: Software Watchdog Timer register Clock Configuration register Address: A090 017C The Clock Configuration register enables and disables clocks to each module on the AHB bus.
Page 318 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Register bit assignment Bits Access D31:10 D09:07 Table 185: Clock Configuration register 2 9 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 319 Reset and Sleep Control register Address: A090 0180 The Reset and Sleep Control register resets each module on the AHB bus. To use sleep mode, the CPU must reset and stop the clocks to all modules not used to wake up the CPU.
Page 320 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Bits Access D15:07 Table 186: Reset and Sleep Control register Miscellaneous System Configuration and Status register Address: A090 0184 2 9 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 321 Reserved CS1DW MCCM PMSS CS1P Rsvd Reset Description Revision Indicates the NS9750 hardware identification and revision. PCI arbiter configuration External PCI arbiter Internal PCI arbiter HW strap Bootup memory mode reset_done Boot from SDRAM using SPI serial EEPROM Boot from Flash/ROM on memory chip select 1 Status only;...
Page 322 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Bits Access D09:08 Table 187: Miscellaneous System Configuration and Status register 2 9 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset...
Page 323 Bits Access Table 187: Miscellaneous System Configuration and Status register PLL Configuration register Address: A090 0188 The PLL Configuration register configures the PLL. Reserved PLLSW Register bit assignment Bits Access D31:26 D24:23 D22:21 Table 188: PLL Configuration register Mnemonic Reset Description IRAM0 Internal register access mode bit 0...
Page 324 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Bits Access D20:16 D14:10 D08:07 D06:05 D04:00 Table 188: PLL Configuration register 3 0 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 325: Timer 0–15 Control Registers
Active Interrupt Level Status register Address: A090 018C The Active Interrupt Level Status register shows the current active interrupt level. Register bit assignment Bits Access D31:06 D05:00 Table 189: Active Interrupt Level Status register Timer 0–15 Control registers Address: A090 0190 / 0194 / 0198 / 019C / 01A0 / 01A4 / 01A8 / 01AC / 01B0 / 01B4 / 01B8 / 01BC / 01C0 / 01C4 / 01C8 / 01CC Use the Timer Control registers to select the source clock frequency, as well as other attributes, for each general purpose timer/counter.
Page 326 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Register bit assignment Bits Access 31:16 D14:10 D08:06 Table 190: Timer Control register 3 0 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 327 Bits Access D05:04 Table 190: Timer Control register System Memory Chip Select 0 Dynamic Memory Base and Mask registers Address: A090 01D0 / 01D4 These control registers set the base and mask for system memory chip select 1, with a minimum size of 4K. The powerup default settings produce a memory range of 0x0000 0000 —...
Page 328 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Chip select 0 base (CS0B) Chip select 0 mask (CS0M) Register bit assignment Bits Access D31:12...
Page 329 Chip select 1 base (CS1B) Chip select 1 mask (CS1M) Register bit assignment Bits Access D31:12 D11:00 D31:12 D11:00 Table 192: System Memory Chip Select 1 Dynamic Memory Base & Mask registers System Memory Chip Select 2 Dynamic Memory Base and Mask registers Address: A090 01E0 / 01E4 These control registers set the base and mask for system memory chip select 6, with a minimum size of 4K.
Page 330 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Chip select 2 base (CS2B) Chip select 2 mask (CS2M) Register bit assignment Bits Access D31:12...
Page 331 Chip select 3 base (CS3B) Chip select 3 mask (CS3M) Register bit assignment Bits Access D31:12 D11:00 D31:12 D11:00 Table 194: System Memory Chip Select 3 Dynamic Memory Base & Mask registers System Memory Chip Select 0 Static Memory Base and Mask registers Address: A090 01F0 / 01F4 These control registers set the base and mask for system memory chip select 0, with a minimum size of 4K.
Page 332 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Chip select 0 base (CS0B) Chip select 0 mask (CS0M) Register bit assignment Bits Access D31:12...
Page 333 Chip select 1 base (CS1B) Chip select 1 mask (CS1M) Register bit assignment Bits Access D31:12 D11:00 D31:12 D11:00 Table 196: System Memory Chip Select 1 Memory Base and Mask registers System Memory Chip Select 2 Static Memory Base and Mask registers Address: A090 0200 / 0204 These control registers set the base and mask for system memory chip select 2, with a minimum size of 4K.
Page 334 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Chip select 2 base (CS2B) Chip select 2 mask (CS2M) Register bit assignment Bits Access D31:12...
Page 335 Chip select 3 base (CS3B) Chip select 3 mask (CS3M) Register bit assignment Bits Access D31:12 D11:00 D31:12 D11:00 Table 198: System Memory Chip Select 3 Static Memory Base & Mask registers Gen ID register Address: A090 0210 This register is read-only, and indicates the state of GPIO pins at powerup. Chip select 3 base (CS3B) Chip select 3 mask (CS3M) Mnemonic...
Page 336 S y s t e m c o n f i g u r a t i o n r e g i s t e r s Register bit assignment Bits Access D31:00 Table 199: General Purpose ID register 3 1 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e GENID...
Page 337: External Interrupt 0–3 Control Register
External Interrupt 0–3 Control register Address: A090 0214 / 0218 / 021C / 0220 The External Interrupt Control registers control the behavior of external interrupts 0–3. The external interrupts are behind GPIO (see "GPIO MUX," beginning on page 34). Register bit assignment Bits Access D31:04...
Page 339: Ethernet Communication
Ethernet Communication Module he Ethernet Communication module consists of an Ethernet Media Access Controller (MAC) and Ethernet front-end module. The Ethernet MAC interfaces to an external PHY through one of two industry-standard interfaces: MII and RMII. The Ethernet front-end module provides all of the control functions to the MAC. 3 1 5...
Page 340: Overview
O v e r v i e w Overview The Ethernet MAC module provides the following: Station address logic (SAL) Statistics module Interface to MII (Media Independent Interface) PHY Interface to RMII (Reduced Media Independent Interface) PHY The Ethernet front-end module does the following: Provides control functions to the MAC Buffers and filters the frames received from the MAC Pumps transmit data into the MAC...
Page 341: Ethernet Mac
E t h e r n e t C o m m u n i c a t i o n M o d u l e Ethernet PHY MGMT Ethernet Ethernet Front End SYSTEM BUS Figure 63: Ethernet Communication module block diagram Ethernet MAC The Ethernet MAC includes a full function 10/100 Mbps Media Access Controller (MAC), station address filtering logic (SAL), statistic collection module (STAT), and...
Page 342 E t h e r n e t M A C TRANSMIT DATA TRANSMIT STATUS SYSTEM RECEIVE INTERFACE DATA MODULE RECEIVE STATUS CONTROL/ STATUS ACCEPT/ REJECT Figure 64: Ethernet MAC block diagram Feature MAC Core HOST CLK & Reset Table 201: Ethernet MAC features 3 1 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e MAC CORE...
Page 343 Table 201: Ethernet MAC features Table 202 shows how the different PHY interfaces are mapped to the external IO. In addition to these signals, NS9750 has a dedicated interrupt input for the external PHY enet_phy_int E t h e r n e t C o m m u n i c a t i o n M o d u l e Note that the NS9750 RMII interface incorrectly handles packets with dribble.
Page 344 Pull low external to NS9750 RXD[2] Pull low external to NS9750 RXD[1] RXD[1] RXD[0] RXD[0] RX_DV Pull low external to NS9750 RX_ER RX_ER Optional signal; pull low external to NS9750 if not being used RX_CLK REF_CLK TXD[3] TXD[2] TXD[1] TXD[1] TXD[0] TXD[0] TX_EN...
Page 345: Station Address Logic (Sal)
Station address logic (SAL) The station address logic module examines the destination address field of incoming frames, and filters the frames before they are stored in the Ethernet front-end module. The filtering options, listed next, are programmed in the Station Address Filter register (see page 366).
Page 346 E t h e r n e t M A C If any of the counters roll over, an associated carry bit is set in the Carry 1 (CAR1) or Carry 2 (CAR2) registers (see "General Statistics registers," beginning on page 377). Any statistics counter overflow can cause the bit in the Ethernet Interrupt STOVFL...
Page 347: Ethernet Front-End Module
Ethernet front-end module Figure 65 shows the Ethernet front-end module (EFE). MAC Host I/F, Stat Host I/F, SAL Host I/F To Receive/Transmit Packet Processors From Receive/Transmit Packet Processors SAL Accept/Reject Rx Status RX_WR -Src Addr Filter -FIFO WR Ctl Rx Ctl Rx Data Tx Status Tx Ctl...
Page 348: Receive Packet Processor
FIFO at the end of the frame, the data FIFO and sets Status register. Power down mode logic supports the NS9750’s system power down and recovery RX_WR functionality. In this mode, the RX clock to the MAC and the active, but the clock to the...
Page 349 to be received and written into the receive FIFO, but the frame remains in the FIFO until the system wakes up. Normal frame filtering is still performed. When a qualified frame is inserted into the receive FIFO, the receive packet processor notifies the system power controller, which performs the wake up sequence.
Page 350 E t h e r n e t f r o n t - e n d m o d u l e used is read from system memory and stored in the registers internal to the logic. OFFSET + 0 OFFSET + 4 OFFSET + 8 OFFSET + C...
Page 351: Transmit Packet Processor
Field Buffer length Transmit packet processor Transmit frames are transferred from system memory to the transmit packet processor into a 256-byte TX_FIFO. Because various parts of the transmit frame can reside in different buffers in system memory, several buffer descriptors can be used to transfer the frame.
Page 352 E t h e r n e t f r o n t - e n d m o d u l e Field Buffer pointer Status Buffer length 3 2 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Description When set, tells the logic to set...
Page 353 Setting the EXTDMA (enable transmit DMA) bit in Ethernet General Control Register #1 starts the transfer of transmit frames from the system memory to the TX_FIFO. The logic reads the first buffer descriptor in the TX buffer descriptor RAM. TX_WR If the F bit is set, it transfers data from system memory to the TX_FIFO using the buffer pointer as the starting point.
Page 354: Ethernet Slave Interface
E t h e r n e t f r o n t - e n d m o d u l e contain the correct value. In this situation, software must keep track of the location of the next buffer descriptor to be kicked off. If the TX_WR logic updates the current buffer descriptor as described in the previous...
Page 355: Interrupts
The slave also generates an AHB boundary, and the Configuration register (see "Miscellaneous System Configuration and Status register," beginning on page 296). In addition, accesses to non-existent addresses result in an response. ERROR Interrupts Separate RX and TX interrupts are provided back to the system. Table 203 shows all interrupt sources and the interrupts to which they are assigned.
Page 356: Resets
E t h e r n e t f r o n t - e n d m o d u l e Interrupt condition Transmit buffer not ready F bit not set in transmit buffer descriptor when read from TX Transmit complete TXERR TXIDLE...
Page 357 Bit field Register RMIIM MII Management Configuration register RPERMII PHY Support register Table 204: Reset control E t h e r n e t C o m m u n i c a t i o n M o d u l e Active Default state...
Page 358: External Cam Filtering
External CAM filtering NS9750 supports external Ethernet CAM filtering, which requires an external CAM controller to operate in conjunction with the MAC inside NS9750. The interface to the CAM controller is provided through GPIO in NS9750. External CAM filtering uses these...
Page 359 RX_CLK RXD[3:0] Preamble/ CAM_REQ 5 RXCLKs CAM_REJECT Figure 68: External Ethernet CAM filtering for MII PHY In this example, the MII receive interface is transferring a frame whose first 6 nibbles have the values 1, 2, 3, 4, 5, and 6. The external CAM hardware uses the signal to find the alignment for the destination address.
Page 360 E x t e r n a l C A M f i l t e r i n g REF_CLK CRS_DV Note 1 RXD[1:0] 1. Rising edge of CRS_DV asynchronous relative to REF_CLK 2. CRS_DV synchronous to REF_CLK once RXD[1:0] changes from "00" to "01"...
Page 361: Ethernet Control And Status Registers
Ethernet Control and Status registers Table 205 shows the address for each Ethernet controller register. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed. Address A060 0000 A060 0004 A060 0008 A060 000C–A060 0014 A060 0018 A060 001C...
Page 362 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Address A060 0448 A060 0500 A060 0504 A060 0508 A060 0680 A060 0A00...
Page 363: Ethernet General Control Register #1
Ethernet General Control Register #1 Address: A060 0000 Rsvd PHY_MODE Rsvd Register bit assignment Bits Access Table 206: Ethernet General Control Register #1 Not used MAC_ Not used ITXA ALIGN HRST Mnemonic Reset Description Enable RX packet processing (see "Receive packet processor"...
Page 364 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D27:24 Table 206: Ethernet General Control Register #1 3 4 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 365 10/100 Mbit RMII mode Reserved Reserved Identifies what type of Ethernet PHY is attached to NS9750. NS9750 supports two styles of Ethernet PHY: MII and RMII. This field should be changed only while the MAC is reset. Always write as 0.
Page 366: Ethernet General Control Register #2
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D07:00 Table 206: Ethernet General Control Register #1 Ethernet General Control Register #2 Address: A060 0004 Register bit assignment...
Page 367 Bits Access Mnemonic TCLER AUTOZ CLRCNT STEN Table 207: Ethernet General Control Register #2 E t h e r n e t C o m m u n i c a t i o n M o d u l e Reset Description Clear transmit error...
Page 368: Ethernet General Status Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Ethernet General Status register Address: A060 0008 Register bit assignment Bits Access...
Page 369 Register bit assignment Bits Access Mnemonic D31:16 Reserved TXOK TXBR TXMC TXAL TXAED Table 209: Ethernet Transmit Status register E t h e r n e t C o m m u n i c a t i o n M o d u l e Reserved used Reset...
Page 370 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access Table 209: Ethernet Transmit Status register 3 4 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 371: Ethernet Receive Status Register
Bits Access D03:00 Table 209: Ethernet Transmit Status register Ethernet Receive Status register Address: A060 001C The Ethernet Receive Status register contains the status for the last completed receive frame. The RXBR bit in the Ethernet Interrupt Status register (see page 385) is set whenever a receive frame is completed and the Ethernet Receive Status register is loaded at the same time.
Page 372: Mac Configuration Register #1
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D08:00 Table 210: Ethernet Receive Status register MAC Configuration Register #1 Address: A060 0400 MAC Configuration Register #1 provides bits that control functionality within the...
Page 373 RPER SRST Reserved used used Register bit assignment Bits Access Mnemonic D31:16 Reserved SRST Not used D13:12 Reserved Not used RPERFUN RPEMCST RPETFUN D07:05 Reserved LOOPBK D03:01 Not used Table 211: MAC Configuration Register #1 E t h e r n e t C o m m u n i c a t i o n M o d u l e Reserved RPET Reserved...
Page 374 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access Mnemonic Reset Description RXEN Receive enable Set this bit to 1 to allow the MAC receiver to receive frames.
Page 375: Mac Configuration Register #2
MAC Configuration Register #2 Address: A060 0404 MAC Configuration Register #2 provides additional bits that control functionality within the Ethernet MAC block. Rsvd used Register bit assignment Bits Access D31:15 D11:10 Table 212: MAC Configuration Register #2 Reserved NOBO Reserved LONGP PUREP AUTOP VLANP PADEN Mnemonic...
Page 376 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access Table 212: MAC Configuration Register #2 3 5 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 377: Pad Operation Table For Transmit Frames
Bits Access Mnemonic HUGE Not used FULLD Table 212: MAC Configuration Register #2 PAD operation table for transmit frames Type AUTOP VLANP PADEN E t h e r n e t C o m m u n i c a t i o n M o d u l e Reset Definition Huge frame enable...
Page 378: Back-To-Back Inter-Packet-Gap Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Back-to-Back Inter-Packet-Gap register Address: A060 0408 Register bit assignment Bits Access D31:07...
Page 379: Non Back-To-Back Inter-Packet-Gap Register
Non Back-to-Back Inter-Packet-Gap register Address: A060 040C Rsvd Register bit assignment Bits Access D31:15 D14:08 D06:00 Table 214: Non Back-to-Back Inter-Packet-Gap register Collision Window/Retry register Address: A060 0410 Reserved IPGR1 Rsvd Mnemonic Reset Description Reserved IPGR1 0x00 Non back-to-back inter-packet-gap part 1 Programmable field indicating optional carrierSense window (referenced in IEEE 8.2.3/4.2.3.2.1).
Page 380 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Reserved Register bit assignment Bits Access D31:14 D13:08 D07:04 D03:00...
Page 381: Maximum Frame Register
Maximum Frame register Address: A060 0414 Register bit assignment Bits Access D31:16 D15:00 Table 216: Maximum Frame register Reserved MAXF Mnemonic Reset Description Reserved MAXF 0x0600 Maximum frame length Default value of frame of 1536 octets. An untagged maximum-size Ethernet frame is 1518 octets.
Page 382: Phy Support Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s PHY Support register Address: A060 0418 RPER Register bit assignment Bits Access...
Page 383: Mii Management Configuration Register
MII Management Configuration register Address: A060 0420 RMIIM Register bit assignment Bits Access D31:16 D14:05 D04:02 Table 218: MII Management Configuration register Reserved Reserved Mnemonic Reset Description Reserved RMIIM Reset MII management block Set this bit to 1 to reset the MII Management module. Reserved CLKS Clock select...
Page 384: Mii Management Command Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Clocks field settings CLKS field MII Management Command register Address: A060 0424 Register bit assignment If both SCAN and READ are set, SCAN takes precedence.
Page 385: Mii Management Address Register
Bits Access Table 219: MII Management Command register MII Management Address register Address: A060 0428 Reserved Register bit assignment Bits Access D31:13 Table 220: MII Management Address register Mnemonic Reset Description SCAN Automatically scan for read data Set to 1 to have the MII Management module perform read cycles continuously.
Page 386: Mii Management Write Data Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D12:08 D07:05 D04:00 Table 220: MII Management Address register MII Management Write Data register Address: A060 042C Register bit assignment...
Page 387: Mii Management Read Data Register
MII Management Read Data register Address: A060 0430 Register bit assignment Bits Access D31:16 D15:00 Table 222: MII Management Read Data register MII Management Indicators register Address: A060 0434 Reserved MRDD Mnemonic Reset Description Reserved MRDD 0x0000 MII read data Read data is obtained by reading from this register after an MII Management read cycle.
Page 388: Station Address Registers
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Register bit assignment Bits Access D31:04 Table 223: MII Management Indicators register Station Address registers Address: A060 0440 / 0444 / 0448 The 48-bit station address is loaded into Station Address Register #1, Station Address...
Page 389 OCTET3 OCTET5 Bits Access Mnemonic Station Address Register #1 D31:16 Reserved D15:08 OCTET1 D07:00 OCTET2 Station Address Register #2 D31:16 Reserved D15:08 OCTET3 D07:00 OCTET4 Station Address Register #3 D31:16 Reserved D15:08 OCTET5 D07:00 OCTET6 Table 224: Station Address registers Octet #6 is the first byte of a frame received from the MAC.
Page 390: Station Address Filter Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Station Address Filter register Address: A060 0500 The Station Address Filter register contains several filter controls.
Page 391 HT1 stores enables for the lower 32 CRC addresses; HT2 stores enables for the upper 32 CRC addresses. Address: A060 0504 Register bit assignment Bits Access Mnemonic D31:00 Table 226: Hash Table Register 1 Address: A060 0508 Register bit assignment Bits Access Mnemonic...
Page 392: Statistics Registers
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Statistics registers Address: A060 0680 (base register) The Statistics module has 39 counters and 4 support registers that count and save Ethernet statistics.
Page 393 Receive statistics counters Address Register A060_069C RBYT A060_06A0 RPKT A060_06A4 RFCS A060_06A8 RMCA A060_06AC RBCA A060_06B0 RXCF A060_06B4 RXPF A060_06B8 RXUO A060_06BC RALN A060_06C0 Reserved A060_06C4 RCDE A060_06C8 RCSE A060_06CC RUND A060_06D0 ROVR A060_06D4 RFRG A060_06D8 RJBR A060-06DC Reserved Table 229: Receive statistics counters address map Receive byte counter (A060 069C) Incremented by the byte count of frames received with 0 to 1518 bytes, including those in bad packets, excluding framing bits but including FCS bytes.
Page 394 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Receive packet counter (A060 06A0) Incremented for each received frame (including bad packets, and all unicast, broadcast, and multicast packets).
Page 395 Receive control frame packet counter (A060 06B0) Incremented for each MAC control frame received (PAUSE and unsupported). D31:12 Reset = Read as 0 D11:00 Reset = 0x000 Receive PAUSE frame packet counter (A060 06B4) Incremented each time a valid PAUSE control frame is received. D31:12 Reset = Read as 0 D11:00...
Page 396 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Receive carrier sense error counter (A060 06C8) Incremented each time a false carrier is found during idle, as defined by a 1 on and an on RXD.
Page 397 increment when a packet is truncated to 1518 (non-VLAN) or 1522 (VLAN) bytes by MAXF. D31:12 Reset = Read as 0 D11:00 Reset = 0x000 Transmit statistics counters Address Register A060_06E0 TBYT A060_06E4 TPKT A060_06E8 TMCA A060_06EC TBCA A060_06F0 Reserved A060_06F4 TDFR A060_06F8...
Page 398 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Transmit byte counter (A060 06E0) Incremented by the number of bytes that were put on the wire, including fragments of frames that were involved with collisions.
Page 399 Transmit excessive deferral packet counter (A060 06F8) Incremented for frames aborted because they were deferred for an excessive period of time (3036 byte times). D31:12 Reset = Read as 0 D11:00 Reset = 0x000 Transmit single collision packet counter (A060 06FC) Incremented for each frame transmitted that experienced exactly one collision during transmission.
Page 400 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Transmit total collision packet counter (A060 070C) Incremented by the number of collisions experienced during the transmission of a frame.
Page 401 Transmit undersize frame counter (A060 0728) Incremented for every frame less than 64 bytes, with a correct FCS value. This counter also is incremented when a jumbo packet is aborted (see "TXAJ" on page 346) and the MAC is not checking the FCS (see "CRCEN" on page 352), because the frame is reported as having a length of 0 bytes.
Page 402 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Carry Register 1 Address: A060 0730 C164 C1127 C1255 C1511 Bits...
Page 403 Bits Access Mnemonic C1RCS C1RUN C1ROV C1RFR C1RJB Reserved Table 232: Carry Register 1 Carry Register 2 Address: A060 0734 C2TMC C2TBC Bits Access Mnemonic D31:20 Reserved C2TJB C2TFC Reserved C2TOV C2TUN C2TFG C2TBY C2TPK C2TMC Table 233: Carry Register 2 E t h e r n e t C o m m u n i c a t i o n M o d u l e Reset Description...
Page 404 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D01:00 Table 233: Carry Register 2 Carry Register 1 Mask register Address: A060 0738 M164 M1127...
Page 405 Bits Access Mnemonic M1MGV D24:17 Reserved M1RBY M1RPK M1RFC M1RMC M1RBC M1RXC M1RXP M1RXU M1RAL Not used M1RCD M1RCS M1RUN M1ROV M1RFR M1RJB Not used Table 234: Carry Register 1 Mask register E t h e r n e t C o m m u n i c a t i o n M o d u l e Reset Description Mask register 1 TRMGV counter carry bit mask...
Page 406 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Carry Register 2 Mask register Address: A060 073C Bits Access D31:20...
Page 407: Rx_A Buffer Descriptor Pointer Register
RX_A Buffer Descriptor Pointer register Address: A060 0A00 Register bit assignment Bits Access D31:00 Table 236: RX_A Buffer Descriptor Pointer register RX_B Buffer Descriptor Pointer register Address: A060 0A04 Register bit assignment Bits Access D31:00 Table 237: RX_B Buffer Descriptor Pointer register RXAPTR RXAPTR Mnemonic...
Page 408: Rx_C Buffer Descriptor Pointer Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s RX_C Buffer Descriptor Pointer register Address: A060 0A08 Register bit assignment Bits Access...
Page 409: Ethernet Interrupt Status Register
Ethernet Interrupt Status register Address: A060 0A10 The Ethernet Interrupt Status register contains status bits for all of the Ethernet interrupt sources. Each interrupt status bit is assigned to either the RX or TX Ethernet interrupt; bits D25:16 are assigned to the RX interrupt and D06:00 are assigned to the TX interrupt.
Page 410 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D15:07 Table 240: Ethernet Interrupt Status register 3 8 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 411: Ethernet Interrupt Enable Register
Bits Access Table 240: Ethernet Interrupt Status register Ethernet Interrupt Enable register Address: A060 0A14 The Ethernet Interrupt Enable register contains individual enable bits for each of the bits in the Ethernet Interrupt Status register. When these bits are cleared, the corresponding bit in the Ethernet Interrupt Status register cannot cause the interrupt signal to the system to be asserted when it is set.
Page 412 E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Reserved Register bit assignment Bits Access D31:26 D15:07 Table 241: Ethernet Interrupt Enable register 3 8 8...
Page 413: Tx Buffer Descriptor Pointer Register
TX Buffer Descriptor Pointer register Address: A060 0A18 Register bit assignment Bits Access D31:08 D07:00 Table 242: TX Buffer Descriptor Pointer register Transmit Recover Buffer Descriptor Pointer register Address: A060 0A1C Reserved Reserved Mnemonic Reset Description Reserved TXPTR 0x00 Contains a pointer to the initial transmit buffer descriptor in the TX buffer descriptor RAM.
Page 414: Tx Error Buffer Descriptor Pointer Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Register bit assignment Bits Access D31:08 D07:00 Table 243: Transmit Recover Buffer Descriptor Pointer register TX Error Buffer Descriptor Pointer register Address: A060 0A20...
Page 415: Rx_A Buffer Descriptor Pointer Offset Register
Bits Access D07:00 Table 244: TX Error Buffer Descriptor Pointer register RX_A Buffer Descriptor Pointer Offset register Address: A060 0A28 Reserved Mnemonic Reset Description TXERBD 0x00 Contains the pointer (in the TX buffer descriptor RAM) to the last buffer descriptor of a frame that was not successfully transmitted.
Page 416: Rx_B Buffer Descriptor Pointer Offset Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Register bit assignment Bits Access D31:11 D10:00 Table 245: RX_A Buffer Descriptor Pointer Offset register RX_B Buffer Descriptor Pointer Offset register Address: A060 0A2C...
Page 417: Rx_C Buffer Descriptor Pointer Offset Register
RX_C Buffer Descriptor Pointer Offset register Address: A060 0A30 Reserved Register bit assignment Bits Access D31:11 D10:00 Table 247: RX_C Buffer Descriptor Pointer Offset register RX_D Buffer Descriptor Pointer Offset register Address: A060 0A34 Reserved Reserved Mnemonic Reset Description Reserved RXCOFF 0x000 Contains an 11-bit byte offset from the start of the pool C...
Page 418: Transmit Buffer Descriptor Pointer Offset Register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s Register bit assignment Bits Access D31:11 D10:00 Table 248: RX_D Buffer Descriptor Pointer Offset register Transmit Buffer Descriptor Pointer Offset register Address: A060 0A38...
Page 419: Rx Free Buffer Register
RX Free Buffer register Address: A060 0A3C So the logic knows when the software is freeing a buffer for reuse, the RX_RD software writes to the RXFREE register each time it frees a buffer in one of the pools. RXFREE has an individual bit for each pool; this bit is set to 1 when the register is written.
Page 420: Tx Buffer Descriptor Ram
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s TX buffer descriptor RAM Address: A060 1000 The TX buffer descriptor RAM holds 64 transmit buffer descriptors on-chip.
Page 421: Sample Hash Table Code
Sample hash table code This sample C code describes how to calculate hash table entries based on 6-byte Ethernet destination addresses and a hash table consisting of two 32-bit registers (HT1 and HT2). HT1 contains locations 31:0 of the hash table; HT2 contains locations 63:32 of the hash table.
Page 422 S a m p l e h a s h t a b l e c o d e // create hash table for MAC address eth_make_hash_table (hash_table); (*MERCURY_EFE) .ht2.bits.data = SWAP32(hash_table[1]); (*MERCURY_EFE) .ht1.bits.data = SWAP32(hash_table[0]); * Function: void eth_make_hash_table (WORD32 *hash_table) * Description: This routine creates a hash table based on the CRC values of the MAC addresses setup by set_hash_bit().
Page 423 set_hash_bit ((BYTE *) hash_table, calculate_hash_bit (mca_address [index])); * Function: void set_hash_bit (BYTE *table, int bit) * Description: This routine sets the appropriate bit in the hash table. * Parameters: table * Return Values: none static void set_hash_bit (BYTE *table, int bit) int byte_index, bit_index;...
Page 424 S a m p l e h a s h t a b l e c o d e * Function: int calculate_hash_bit (BYTE *mca) * Description: This routine calculates which bit in the CRC hash table needs to be set for the MERCURY to recognize incoming packets with the MCA passed to us.
Page 425 mcap++; for (bit_index = 0; bit_index < 16; bit_index++) bx = (WORD16) (crc >> 16); bx = rotate (bx, LEFT, 1); bx ^= bp; crc <<= 1; bx &= 1; if (bx) crc ^= POLYNOMIAL; crc |= bx: bp = rotate (bp, RIGHT, 1); // CRC calculation done.
Page 426 S a m p l e h a s h t a b l e c o d e 4 0 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 427 PCI-to-AHB Bridge he PCI-to-AHB bridge provides connections between PCI-based modules/devices and the NS9750 AHB bus. This chapter presumes knowledge of PCI system standards and Important: architecture, and explains how PCI works in relation to the AHB bus. If you have questions regarding PCI terminology or concepts, please refer to your PCI documentation.
Page 428: About The Pci-To-Ahb Bridge
A b o u t t h e P C I - t o - A H B B r i d g e About the PCI-to-AHB Bridge The PCI-to-AHB bridge provides these features: Supports PCI specification 2.1 and 2.2 protocol AHB master and slave interfaces PCI master and target interfaces Open drain interrupt output for PCI bus...
Page 429: Pci-To-Ahb Bridge Functionality
PCI-to-AHB bridge functionality Figure 71 shows the PCI-to-AHB bridge. Downstream transactions are those initiated on the AHB bus; upstream transactions are those initiated on the PCI bus. Bus/ grant Figure 71: PCI-to-AHB bridge diagram AHB master interface The AHB master interface block controls the bridge’s access to the AHB bus as a master, and is used for reads and writes to the AHB bus that are initiated on the PCI bus by an external PCI bus master.
Page 430 A b o u t t h e P C I - t o - A H B B r i d g e being sent back to the PCI bus. The AHB master interface supports both single and burst transactions. AHB slave/target interface The AHB slave/target interface block controls the AHB target access to the bridge, and is used for reads and writes to the PCI bus that are initiated on the AHB bus.
Page 431: Cross-Bridge Transaction Error Handling
PCI bus arbiter The PCI bus arbiter (also referred to as PCI arbiter), although embedded in NS9750, is not part of the PCI-to-AHB bridge protocol. See "PCI bus arbiter," beginning on page 418, for information about the PCI arbiter. The arbiter’s use is optional.
Page 432: Ahb Address Decoding And Translation
A b o u t t h e P C I - t o - A H B B r i d g e DETECTED PARITY ERROR SIGNALED TARGET ABORT For data parity checking on writes, the entire burst is discarded if any word in the burst has a parity error.
Page 433: Interrupts
When set to 0, no address translation takes place, and the AHB and PCI addresses are identical. The external PCI bus is allowed access only to NS9750’s system memory. The values, therefore, should be programmed only to map addresses in the MALTxVAL lower 2 GB of NS9750’s 4 GB address space (...
Page 434: Transaction Ordering
The bridge can drive an interrupt to the PCI bus. This interrupt is driven from the bit in the PCI Miscellaneous Support register (see page 426) in the PCI arbiter. INTA2PCI This interrupt is used only in systems in which NS9750 is not processing PCI interrupts, and is set by software. Transaction ordering The AHB-to-PCI bridge maintains the request order in each direction.
Page 435: Endian Configuration
Endian configuration The PCI bus is defined as little endian and the AHB bus can be defined as either Big or little endian. The PCI-to-AHB bridge supports byte-swapping only when the AHB bus is configured as a big endian bus. Byte-swapping is selected using the endian mode bit in the Miscellaneous System Configuration register (see "Miscellaneous System Configuration and Status register,"...
Page 436 A b o u t t h e P C I - t o - A H B B r i d g e Bits Access D23:16 D15:11 D10:08 D07:02 D01:00 Table 253: CONFIG_ADDR register 4 1 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 437: Bridge Configuration Registers
Bridge Configuration registers Table 254 shows the standard PCI configuration registers that are supported by the PCI-to-AHB bridge. These registers can be 8-, 16-, or 32-bits wide, as indicated in the table. The size of the transfer on the AHB bus determines which bytes are written. All configuration registers must be accessed as 32-bit words and as single accesses only.
Page 438 SERR# Address stepping Parity error response VGA palette snooping Master MWI (set to 0 for NS9750) Special cycle response Bus master (set to 1 for NS9750) Memory enable (set to 1 for NS9750) IO enable (set to 0 for NS9750)
Page 439 PCI Status register Table 256 describes the PCI Status register fields. Bits Access Mnemonic SERR# D10:09 Hard-wired DEVSEL to 10 PERR# Table 256: PCI Status register Reset Description Detected parity error Device detected parity error. Used as an interrupt source to AHB bus.
Page 440 A b o u t t h e P C I - t o - A H B B r i d g e Bits Access Hard-wired to 1 Hard-wired to 0 D04:00 Table 256: PCI Status register PCI Revision ID register Read-only value.
Page 441 PCI BIST register Read-only value, hardwired to PCI Base Address registers [5:0] The PCI-to-AHB bridge supports the six Base Address registers defined by PCI. Table 257 defines the memory space size decoded by each register. Base Address register Memory size decoded 256 MB 64 MB 16 MB...
Page 442: Pci Bus Arbiter
(see page 431) in the PCI arbiter. PCI bus arbiter NS9750 provides an embedded PCI bus arbiter that supports up to three external PCI masters and the internal PCI-to-AHB bridge. The arbiter uses a rotating priority scheme. An AHB slave is integrated with the PCI bus arbiter to access programmable registers, to support system configuration and error reporting.
Page 443: Pci Arbiter Functional Description
NS9750 can be configured to use either the embedded PCI arbiter or an external arbiter through the bootstrap initialization scheme used during powerup (see "Bootstrap initialization" on page 272). The The internal arbiter is used if If a pulldown resistor is placed on the...
Page 444: Slave Interface
P C I b u s a r b i t e r If there are no new requesters when the current bus master completes its transaction, the bus ownership stays with the most recent bus master (bus parking). If a is asserted from any of the other masters, there must be a one clock cycle REQ# delay between the negation of the...
Page 445 Address Offset Register 0xA030 0000 PARBCFG 0xA030 0004 PARBINT 0xA030 0008 PARBINTEN 0xA030 000C PMISC 0xA030 0010 PCFG0 0xA030 0014 PCFG1 0xA030 0018 PCFG2 0xA030 001C PCFG3 0xA030 0020 PAHBCFG 0xA030 0024 PAHBERR 0xA030 0028 PCIERR 0xA030 002C PINTR 0xA030 0030 PINTEN 0xA030 0034 PALTMEM0...
Page 446 P C I b u s a r b i t e r Address Offset Register Description 0xA030 1014–0xA030 1FFC Reserved (all read accesses return 0x0 value) Table 259: PCI arbiter register map 4 2 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 447 PCI Arbiter Configuration register Address: A030 0000 The PCI Arbiter Configuration register enables and disables each of the three external PCI bus masters. The internal PCI-to-AHB bridge is always enabled. Register bit assignment Bits Access Mnemonic D31:04 Read only; Reserved hard-wired to 0 PCIEN_M3...
Page 448 (NS9750 has internal pulldown) asserted for 1 clock cycle). There is a separate bit SERR# Reserved Reserved Mnemonic Reset Description Reserved NS9750 provides PCI central resource functions (pulldown) NS9750 does not provide PCI central resource functions CCLK BRK_ BRK_ BRK_ SERR BRK_...
Page 449 Bits Access Mnemonic CCLKRUN PCISERR PCIBRK_M3 PCIBRK_M2 PCIBRK_M1 PCIBRK_M0 Table 261: PCI Arbiter Interrupt Status register PCI Arbiter Interrupt Enable register Address: A030 0008 The PCI Arbiter Interrupt Enable register has an enable bit for each of the interrupt status bits in the PCI Arbiter Interrupt Status register. Set these bits to 1 to allow the associated interrupt status bit to cause an interrupt to the system.
Page 450 The PCI Miscellaneous Support register contains miscellaneous PCI functions that are required in NS9750. Change the PCI activity. In a system where NS9750 is not the host, the programmed within 2 allowed from 4 2 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 451 Reserved Register bit assignment Bits Access Mnemonic D31:10 Read only; Reserved hard-wired to EN_BAR5 EN_BAR4 EN_BAR3 Table 263: PCI Miscellaneous Support register Reserved BAR5 BAR4 BAR3 BAR2 BAR1 Reset Description Enable bridge PCI Base Address register 5 Disable (default) Enable Note: Although when...
Page 452 INTA# high impedance (default) INTA# must be in high impedance state for CardBus applications and for PCI applications when NS9750 is the host, and provides the interrupt controller for PCI interrupts. Assert INTA# low Although can still be accessed...
Page 453 Change these fields only during system initialization, when there is no PCI activity. In a system where NS9750 is not the host, these fields must be programmed within 2 PCI clocks of being negated. This is the time allowed from RST# first configuration cycle on the PCI bus.
Page 454 Subsystem ID and PCI Subsystem Vendor ID registers. Change these fields only during system initialization, when there is no PCI activity. In a system where NS9750 is not the host, these fields must be programmed within 2 PCI clocks of RST# first configuration cycle on the PCI bus.
Page 455 Max_Lat, PCI Min_Gnt, and PCI Interrupt Pin registers. Change these fields only during system initialization, when there is no PCI activity. In a system where NS9750 is not the host, these fields must be programmed within 2 PCI clocks of being negated.
Page 456 The PCI Bridge Configuration register controls the bandwidth allocated to the bridge. Change the AHBBRST or from the bridge. Because the setting of this register affects NS9750’s bandwidth allocation, changes will have an effect on system performance. Register bit assignment...
Page 457 Bits Access Mnemonic D01:00 AHBBRST Table 268: PCI Bridge Configuration register PCI Bridge AHB Error Address register Address: A030 0024 The PCI Bridge AHB Error Address register stores the address of the AHB transaction that received an AHB ERROR response. Register bit assignment Bits Access...
Page 458 P C I b u s a r b i t e r The PCI Bridge PCI Error Address register stores the address of the PCI transaction that received a PCI bus error response. Register bit assignment Bits Access D31:00 Table 270: PCI Bridge PCI Error Address register PCI Bridge Interrupt Status register Address: A030 002C...
Page 459 Register bit assignment Bits Access Mnemonic D31:01 Hardwired to Reserved AHBERR Table 271: PCI Bridge Interrupt Status register PCI Bridge Interrupt Enable register Address: A030 0030 The PCI Bridge Interrupt Enable register stores the enables for all interrupt sources. PSYS PRXT PSIG EREN...
Page 460 P C I b u s a r b i t e r Bits Access D10:09 Hardwired to D07:01 Hardwired to Table 272: PCI Bridge Interrupt Enable register 4 3 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 461 PCI Bridge AHB to PCI Memory Address Translate 0 register Address: A030 0034 The PCI Bridge AHB-to-PCI Memory Address Translate 0 register translates the AHB addresses sent to the PCI-to-AHB bridge to the appropriate PCI memory addresses. Rsvd PALT3VAL Rsvd PALT1VAL Register bit assignment Bits...
Page 462 P C I b u s a r b i t e r PCI Bridge AHB to PCI Memory Address Translate 1 register Address: A030 0038 The PCI Bridge AHB-to-PCI Memory Address Translate 1 register translates the AHB addresses sent to the PCI-to-AHB bridge to the appropriate PCI memory addresses. Rsvd Rsvd Register bit assignment...
Page 463 PCI Bridge AHB-to-PCI IO Address Translate register Address: A030 003C The PCI Bridge AHB-to-PCI IO Address Translate register translates the AHB addresses sent to the PCI-to-AHB bridge to the appropriate PCI IO addresses. Reserved Register bit assignment Bits Access Mnemonic D31:12 Hardwired to Reserved...
Page 464 P C I b u s a r b i t e r Register bit assignment Bits Access D31:30 Hardwired to D29:20 D19:12 D11:10 Hardwired to D09:04 D03:00 Table 276: PCI Bridge PCI-to-AHB Memory Address Translate 0 register PCI Bridge PCI to AHB Memory Address Translate 1 Address: A030 0044 The PCI Bridge PCI-to-AHB Memory Translate 1 register translates the PCI memory addresses to the appropriate AHB memory addresses.
Page 465 Bits Access Mnemonic D25:12 MALT5VAL D11:00 MALT4VAL Table 277: PCI Bridge PCI-to-AHB Memory Address Translate 1 register PCI Bridge Address Translation Control register Address: A030 0048 The PCI Bridge Address Translation Control register controls the address translation process in both direction (AHB-to-PCI and PCI-to-AHB). Register bit assignment Bits Access...
Page 466 CardBus Miscellaneous Support register Address: A030 004C The CardBus Miscellaneous Support register is used for CardBus applications only, and provides NS9750-specific CardBus control and status. (See the NS9750 Sample Driver Configurations for examples of how this register is used.) CMS_...
Page 467 Bits Access Mnemonic CMS_V3_SKT CMS_V5_SKT Hard- Reserved wired to 0 CMS_YV_CARD CMS_XV_CARD CMS_V3_CARD CMS_V5_CARD CMS_BAD_VCC_REQ Table 279: CardBus Miscellaneous Support register P C I - t o - A H B B r i d g e Reset Description Allows software to control the V3_SKT bit in the CardBus Socket Present State register.
Page 468 P C I b u s a r b i t e r Bits Access Table 279: CardBus Miscellaneous Support register 4 4 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset CMS_DATA_LOST...
Page 469 Bits Access Mnemonic CMS_CCD1 D14:11 Hard- Reserved wired to 0 REQ_INTGT_EN REQ_INTGATE INTERROGATE Hard- Reserved wired to 0 CCLKRUN_EN CVS2 Table 279: CardBus Miscellaneous Support register P C I - t o - A H B B r i d g e Reset Description Allows the software to control the CCD1 bit...
Page 470 P C I b u s a r b i t e r Bits Access Table 279: CardBus Miscellaneous Support register CardBus Socket Event register Address: A030 1000 The CardBus Socket Event register is used for CardBus applications only, and indicates a change in socket status.
Page 471 Bits Access Mnemonic D31:04 Hardwired to Reserved PWR_CHG CCD2_CHG CCD1_CHG CSTSCHG_CHG Table 280: CardBus Socket Event register CardBus Socket Mask register Address: A030 1004 The CardBus Socket Mask register is used for CardBus applications only, and contains the interrupt enable bits for each of the bits in the CardBus Socket Event register. P C I - t o - A H B B r i d g e Reset Description...
Page 472 P C I b u s a r b i t e r Register bit assignment Bits Access D31:04 Hardwired to 0 Table 281: CardBus Socket Mask register CardBus Socket Present State register Address: A030 1008 The CardBus Socket Present State register is used for CardBus applications only, and contains status information about the CardBus socket.
Page 473 When set, this bit indicates that supplied to the socket. Zoomed video support Always set to 0, as NS9750 does not support this bit. When set, indicates that the card inserted into the socket supports This bit can also be set by writing a 1 to the FYV_CARD bit in the CardBus Socket Force Event register.
Page 474 P C I b u s a r b i t e r Bits Access Table 282: Cardbus Socket Present State register 4 5 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 475 Bits Access Mnemonic CARD_16 PWR_CYC CCD2 CCD1 CSTSCHG Table 282: Cardbus Socket Present State register CardBus Socket Force Event register Address: A030 100C The CardBus Socket Force Event register is used for CardBus applications only. This register is implemented only as an address that is written to force various status and event bits in the CardBus host bridge through software.
Page 476 P C I b u s a r b i t e r FYV_ Rsvd TEST CARD Register bit assignment Bits Access D31:15 Table 283: CardBus Socket Force Event register 4 5 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Reserved FBAD_ FXV_...
Page 477 Bits Access Mnemonic Reserved FCB_CARD FCARD_16 FPWR_CHG FCCD2_CHG FCCD1_CHG FCSTSCHG_CHG Table 283: CardBus Socket Force Event register P C I - t o - A H B B r i d g e Reset Description Sets the CB_CARD bit in the CardBus Socket Present State register.
Page 478 P C I b u s a r b i t e r CardBus Socket Control register Address: A030 1010 The CardBus Socket Control register is used only for CardBus applications. Reserved Register bit assignment Bits Access D31:12 Hardwired to 0 Hardwired to 0 Hardwired...
Page 479 Bits Access Mnemonic D02:00 VPP_CTL Table 284: CardBus Socket Control register P C I - t o - A H B B r i d g e Reset Description Socket VPP/Core control 12 V 3.3 V Reserved Reserved 1.8 V Reserved w w w .
Page 480: Pci System Configurations
NS9750 can be connected to the PCI bus using an embedded (internal) or external PCI bus arbiter. Figure 72 shows how NS9750 is connected to the PCI bus for a typical system application using the embedded PCI bus arbiter, and where the NS9750 provides the central resource function (see "PCI central resource functions"...
Page 481 RTCK required to select the internal PCI arbiter. Figure 73 shows how NS9750 is connected to the PCI bus for a typical application using an external PCI bus arbiter, and where the NS9750 does not provide the PCI central resource functions (see "PCI central resource functions" on page 458).
Page 482: Device Selection For Configuration
IDSEL the bridge’s configuration registers are being programmed using the AHB bus, NS9750 must be set as Device 0 (see Figure 72, "System connections to NS9750 — Internal arbiter and central resources," on page 456, which shows and which configures NS9750 as PCI Device 0).
Page 483 P C I - t o - A H B B r i d g e , and are driven low when RST# is asserted, to keep the AD[31:0] C/BE[3:0] signals from floating. 4 5 9 w w w . d i g i e m b e d d e d . c o m...
Page 484 GNT# system (because they are tri-stated during The PCI clock can be either generated from NS9750 (see Figure 72, "System connections to NS9750 — Internal arbiter and central resources," on page 456) or provided by an external source (see Figure 73, "System connections to NS9750 —...
Page 485: Cardbus Support
Note that in cases where NS9750 provides the PCI clock, the PCI clock Important: connection to the NS9750 must still be made external to the NS9750, as shown in Figure 73 (that is, connect minimize the clock skew between the NS9750 and external PCI devices.
Page 486 RTCK PCI_CENTRAL_RSC_n BOOT_STRAP[1] GPIO GPIO Figure 74: CardBus system connections to NS9750 4 6 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e RCCD2 RCCD1...
Page 487: Configuring Ns9750 For Cardbus Support
Output Grant to external CardBus device from NS9750’s internal arbiter. Output Voltage sense pin. Normally driven low by NS9750, but toggled during interrogation of external CardBus device to detect voltage requirements. Output Voltage sense pin. Normally driven low by NS9750 but toggled during interrogation of external CardBus device to detect voltage requirements.
Page 488: Cardbus Adapter Requirements
PC I. CardBus adapter requirements In a CardBus application, NS9750 is the adapter, or bridge. The adapter is required to have a set of socket registers that provide socket control and status. The following...
Page 489: Cardbus Interrupts
CardBus Socket Event (see "CardBus Socket Event register" on page 446) CardBus Socket Mask (see "CardBus Socket Mask register" on page 447) CardBus Socket Present State (see "CardBus Socket Present State register" on page 448) CardBus Socket Force Event (see "CardBus Socket Force Event register" on page 451) CardBus Socket Control (see "CardBus Socket Control register"...
Page 490 C a r d B u s S u p p o r t 4 6 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 491 AMBA AHB bus. The low speed peripherals reside on the Digi proprietary BBus. The main function of the BBus bridge is to connect the main AHB bus to the proprietary Digi BBus. Both bus interfaces have a master and a slave interface.
Page 492: Bbus Bridge Functions
B B u s b r i d g e f u n c t i o n s BBus bridge functions The Digi BBus is a low-speed secondary bus that operates at half the AHB clock frequency. The BBus interface houses the slower serial interfaces for USB, IEEE 1284, SPI, and UART, as well as dedicated BBus DMA control, to offload some of the bandwidth demands of the primary AHB bus.
Page 493: Bridge Control Logic
The AHB bus can operate at a maximum of 100MHz; the BBus operates at half the AHB clock frequency. Figure 76 details BBus bridge control logic. NS9750 ASIC ..AHB Module B AHB Module N...
Page 494 B r i d g e c o n t r o l l o g i c AMBA AHB Bus AHB Slave 1 Entry Retiming Fifo BBUS Master NetSilicon BBUS Figure 76: BBus bridge block diagram Notes: The AHB bus and BBus clock domains are asynchronous to each other. A 4-entry bidirectional FIFO is implemented in the BBus-to-AHB data path to allow burst transfers.
Page 495: Dma Accesses
DMA accesses There are two DMA controllers on the NS9750 BBus. One DMA controller services all BBus peripherals except the USB device; the other is dedicated to the USB device. Each DMA controller contains 16 channels that perform both DMA read and DMA write transactions.
Page 496: Bbus Control Logic
B B u s c o n t r o l l o g i c BBus control logic BBus control logic consists of a round-robin arbiter to select a new master, the multiplexing logic to provide the new master’s signals to the BBus slaves, and address decoding to select the target BBus slave.
Page 497: Cycles And Bbus Arbitration
Cycles and BBus arbitration During a normal cycle, each bus master cycle is allowed only one read/write cycle if another bus master is waiting. There are two exceptions to this rule: burst transactions and read-modify-write transactions. In a burst transaction, the master can perform more than one read or write cycle. In a read-modify-write transaction, the bus master performs one read and write cycle to the same location.
Page 498: Two-Channel Ahb Dma Controller (Ahb Bus)
DMA buffer descriptor All DMA channels in NS9750 use a buffer descriptor. When a DMA channel is activated, it reads the DMA buffer descriptor pointed to by the Buffer Descriptor Pointer register (see "Buffer Descriptor Pointer register" on page 491). A DMA buffer descriptor is always fetched using an AHB INCR4 transaction, to maximize AHB bus bandwidth.
Page 499 When the current descriptor is retired, the next descriptor is accessed from a circular buffer. Each DMA buffer descriptor requires four 32-bit words to describe a transfer. Circular buffers of 1024 bytes contain multiple buffer descriptors. The first buffer descriptor address is provided by the DMA channel’s Buffer Descriptor Pointer register.
Page 500: Descriptor List Processing
T w o - c h a n n e l A H B D M A c o n t r o l l e r ( A H B b u s ) Field/Section Reserved Status Table 289: BBus bridge DMA buffer descriptor definition Descriptor list processing When a DMA controller has completed the operation specified by the current buffer descriptor, the controller clears the F bit and fetches the next buffer descriptor.
Page 501: Peripheral Dma Read Access
236). DMA read accesses from an external peripheral are treated as asynchronous operations by the NS9750. It is critical that the required width of the computed correctly and programmed into the Static Memory Read Delay register. Total access time can be computed as shown:...
Page 502: Peripheral Dma Write Access
T w o - c h a n n e l A H B D M A c o n t r o l l e r ( A H B b u s ) READ_EN Figure 79: Peripheral DMA burst read access Peripheral DMA write access Figure 80 and Figure 81 show how the DMA engine performs write accesses of an external peripheral.
Page 503: Peripheral Req Signaling
Figure 81: Peripheral DMA burst write access Peripheral REQ signaling An external peripheral indicates that it can accept or provide data by asserting its REQ signal. The AHB DMA controller fully processes one buffer descriptor for each assertion of the external peripheral’s REQ signal. The AHB DMA controller state machine executes these steps for each assertion of the REQ signal.
Page 504: Design Limitations
(see "Calculating AHB DMA response latency" on page 480). The REQ signal is an asynchronous input to the NS9750. For a REQ signal assertion to be found by the control logic, it must be asserted for no less than 4 AHB clock cycles and no more than 20 AHB clock cycles.
Page 505 transferring data in non-DMA mode do not contribute to the calculation. The worst case AHB DMA response latency occurs when all of the BBus peripherals perform these operations within several microseconds of each other: Move the remaining data in or out of the data buffer. Close the buffer descriptor.
Page 506: Static Ram Chip Select Configuration
T w o - c h a n n e l A H B D M A c o n t r o l l e r ( A H B b u s ) Static RAM chip select configuration The AHB DMA controller accesses an external peripheral using the external memory bus and one of the static RAM chip select signals (st_cs_n[N]).
Page 507: Interrupt Aggregation
Interrupt aggregation All the peripherals on the BBus, as well as AHB DMA channels 1 and 2 in the BBus bridge, can interrupt the CPU when attention is required. These interrupts are aggregated in the BBus bridge, and a single interrupt is presented to the System Control Module on the This function is performed in the BBus bridge because it allows the processor to quickly identify which BBus peripheral(s) is requesting attention.
Page 508: Spi-Eeprom Boot Logic
Table 291 shows the related boot settings. boot_cfg [1:0] Table 291: NS9750 boot configuration When enabled, the boot logic copies the contents of an SPI-EEPROM to system memory, allowing you to boot from a low-cost serial memory. The boot logic works by interfacing to SER port B using the BBus —...
Page 509: Serial Channel B Configuration
Calculation and example This equation calculates the amount of time, in seconds, required to copy the contents of the SPI-EEPROM to external memory: Time = (1 / freq) * EEPROM Example SPI master clock frequency = 1.5 MHz SPI-EEPROM = 256 Kb Time for operation to complete = 175 ms Serial Channel B configuration When exiting the power-on reset state, serial channel B is in SPI master mode, which...
Page 510: Memory Controller Configuration
S P I - E E P R O M b o o t l o g i c Memory Controller configuration See your ARM documentation for complete information about the memory Note: controller. The memory controller exits the reset state in non-operational mode. This requires the SPI-EEPROM boot logic to configure the memory controller as well as the external SDRAM before any memory access.
Page 511 EEPROM entry SDRAM config Config register DynamicRefresh DynamicReadConfig DynamictRP DynamictRAS DynamictSREX DynamictAPR DynamictDAL DynamictWR DynamictRC DynamictRFC DynamictXSR DynamictRRD DynamictMRD Table 293: ARM boot configuration Description All SDRAM components contain a Mode register, which has control information required to successfully access the component. The fields (available in any SDRAM specification) are defined as follows: Burst length: 4 for 32-bit data bus, 8 for 16-bit data bus Burst type: Sequential...
Page 512: Sdram Boot Algorithm
S P I - E E P R O M b o o t l o g i c EEPROM entry DynamicConfig0 DynamicRasCas0 Reserved Boot code Table 293: ARM boot configuration SDRAM boot algorithm The SDRAM boot logic communicates only with serial channel B. Note: These steps describe the SDRAM boot algorithm: Pins...
Page 513 The state machine enters a loop where four NOP words are written to the Fifo Data register and four words are read from the Fifo Data register. The RXFDB and RRDY fields are continuously monitored in Status Register A. The Fifo Data register is read only when a valid word is present.
Page 514: Bbus Bridge Control And Status Registers
B B u s B r i d g e C o n t r o l a n d S t a t u s r e g i s t e r s BBus Bridge Control and Status registers The BBus configuration registers are located at base address configuration registers are accessed with zero wait states.
Page 515: Buffer Descriptor Pointer Register
Buffer Descriptor Pointer register Address: A040 0000 / 0020 This register contains a 32-bit pointer to the first buffer descriptor in a contiguous list of buffer descriptors. The BBus bridge contains a Buffer Descriptor Pointer register for each DMA channel; each register is 16 bytes in length. Register bit assignment Bit(s) Access...
Page 516 B B u s B r i d g e C o n t r o l a n d S t a t u s r e g i s t e r s Register bit assignment Bit(s) Access D28:27 D26:25 Table 297: DMA Channel 1/2 Control register bit definition...
Page 517 Bit(s) Access Mnemonic D24:23 D22:21 SINC_N DINC_N D18:16 MODE Table 297: DMA Channel 1/2 Control register bit definition Reset Description Source burst 2 (Recommended for 8-bit devices) 4 (Recommended for 16-bit devices) 8 (Recommended for 32-bit devices) Defines the AHB maximum burst size allowed when reading from the source.
Page 518: Dma Status And Interrupt Enable Register
B B u s B r i d g e C o n t r o l a n d S t a t u s r e g i s t e r s Bit(s) Access D15:10 D09:00 Table 297: DMA Channel 1/2 Control register bit definition DMA Status and Interrupt Enable register Address: A040 0008 / 0028 The DMA Status and Interrupt Enable register contains the DMA transfer status and...
Page 519 Register bit assignment Bits Access Mnemonic RW1TC NCIP RW1TC ECIP RW1TC NRIP RW1TC CAIP Table 298: DMA Status and Interrupt Enable register bit definition Reset Description Normal completion interrupt pending Set when a buffer descriptor has been closed. A normal DMA completion occurs when the BLEN count expires to 0 and the L bit in the Buffer descriptor is set, or when the peripheral device signals completion.
Page 520: Dma Peripheral Chip Select Register
B B u s B r i d g e C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access RW1TC D26:25 D15:00 Table 298: DMA Status and Interrupt Enable register bit definition DMA Peripheral Chip Select register Address: A040 000C / 002C...
Page 521 Register bit assignment Bits Access Mnemonic D31:04 Not used Not used D01:00 Table 299: DMA Peripheral Chip Select register Not used Not used Reset Description Always set to 0. Chip select polarity Defines the polarity of the memory interface chip select signal ( ) connected to the external peripheral.
Page 522: Bbus Bridge Interrupt Status Register
B B u s B r i d g e C o n t r o l a n d S t a t u s r e g i s t e r s BBus Bridge Interrupt Status register Address: A040 1000 This register contains the interrupt status of the BBus peripherals.
Page 523: Bbus Bridge Interrupt Enable Register
Bits Access Table 300: BBus Bridge Interrupt Status register BBus Bridge Interrupt Enable register Address: A040 1004 The BBus Bridge Interrupt Enable register allows you to enable or disable BBus interrupts on an individual basis as well as a global basis. Writing a 1 to a bit enables the interrupt, allowing it to be included in the aggregate signal that is sent to the vector interrupt controller in the System Control module.
Page 524 B B u s B r i d g e C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D23:13 Table 301: BBus Bridge Interrupt Enable register bit definition 5 0 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 525 BBus DMA Controller he NS9750 ASIC BBus subsystem contains two DMA controllers, each with 16 channels. These DMA controllers are different than the AHB DMA controllers Note: discussed in the BBus Bridge chapter. 5 0 1...
Page 526: About The Bbus Dma Controllers
A b o u t t h e B B u s D M A c o n t r o l l e r s About the BBus DMA controllers There are two BBus DMA controllers. One DMA controller supports all BBus peripherals except the USB device;...
Page 527: Dma Context Memory
Figure 83 shows the BBus DMA controller block. Channel Transfer Attributes BBUS Figure 83: DMA controller block Each DMA controller arbiter determines in which channel the state machine currently is operating. DMA context memory Each DMA controller maintains state for all 16 channels using an on-chip SRAM known as the context memory.
Page 528: Dma Buffer Descriptor
D M A b u f f e r d e s c r i p t o r Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Table 302: DMA context memory entry DMA buffer descriptor All DMA channels operate using a buffer descriptor. Each DMA channel remains idle until enabled through the DMA Channel Control register.
Page 529 OFFSET + 0 OFFSET + 4 Reserved OFFSET + 8 OFFSET + C Figure 84: DMA buffer descriptor Field Description Source address Identifies the starting location of the source data buffer. For transmit buffers. The source address can start on any byte boundary. For receive buffers.
Page 530 D M A b u f f e r d e s c r i p t o r Field Reserved Status Table 303: DMA buffer descriptor definition DMA transfer status The DMA buffer descriptor status field is updated when the buffer descriptor is retired.
Page 531 Bits Mnemonic MATCH1 MATCH2 MATCH3 MATCH4 BGAP CGAP 09:04 UNUSED RBRK ROVER Table 304: Peripheral bit fields: Serial controller — UART RX mode Bits Mnemonic MATCH1 MATCH2 MATCH3 MATCH4 11:00 UNUSED Table 305: Peripheral bit fields: Serial controller — SPI RX mode Bits Mnemonic 15:00...
Page 532 D M A b u f f e r d e s c r i p t o r Bits 15:00 Table 307: Peripheral bit fields: Serial controller — SPI TX mode Bits 15:14 11:00 Table 308: Peripheral bit fields: USB device controller Bits 15:00 Table 309: Peripheral bit fields: IEEE 1284 controller...
Page 533: Dma Channel Assignments
DMA channel assignments Each BBus DMA controller contains 16 DMA channels. Controller DMA1 is dedicated to the BBus peripherals. Controller DMA2 is dedicated to the USB device endpoints. Any given DMA channel is hard-wired to a peripheral. Table 310 indicates which peripherals are hard-wired to which DMA channels, and the DMA mode (direction) required for each.
Page 534: Dma Control And Status Registers
D M A C o n t r o l a n d S t a t u s r e g i s t e r s Channel DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2 DMA2...
Page 535 within each DMA module. The offsets allow address bits [08:05] to encode the DMA channel number. Offset 9000 0000 / 9011 0000 9000 0020 / 9011 0020 9000 0040 / 9011 0040 9000 0060 / 9011 0060 9000 0080 / 9011 0080 9000 00A0 / 9011 00A0 9000 00C0 / 9011 00C0 9000 00E0 / 9011 00E0...
Page 536: Dma Buffer Descriptor Pointer
D M A C o n t r o l a n d S t a t u s r e g i s t e r s Offset 9000 0130 / 9011 0130 9000 0150 / 9011 0150 9000 0170 / 9011 0170 9000 0190 / 9011 0190 9000 01B0 / 9011 01B0 9000 01D0 / 9011 01D0...
Page 537 9000 0000 / 0020 / 0040 / 0060 / 0080 / 00A0 / 00C0 / 00E0 / 0100 / 0120 / 0140 / 0160 / 0180 / 01A0 / 01C0 / 01E0 Address: DMA2 9011 0000 / 0020 / 0040 / 0060 / 0080 / 00A0 / 00C0 / 00E0 / 0100 / 0120 / 0140 / 0160 / 0180 / 01A0 / 01C0 / 01E0 The DMA Buffer Descriptor Pointer register contains a 32-bit pointer to the first buffer descriptor in a contiguous list of buffer descriptors.
Page 538: Dma Control Register
D M A C o n t r o l a n d S t a t u s r e g i s t e r s DMA Control register Address: DMA1 9000 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 00F0 / 0110 / 0130 / 0150 / 0170 / 0190 / 01B0 / 01D0 / 01F0 Address: DMA2 9011 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 00F0 / 0110 / 0130 /...
Page 539 Bits Access Mnemonic D27:26 MODE D25:24 SINC_N D20:18 Not used D17:16 SIZE Table 313: BBus DMA Control register bit definition B B u s D M A C o n t r o l l e r Reset Description Fly-by mode Fly-by write (peripheral-to-memory) Fly-by read (memory-to-peripheral) Undefined...
Page 540: Dma Status/Interrupt Enable Register
D M A C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access D15:10 D09:00 Table 313: BBus DMA Control register bit definition DMA Status/Interrupt Enable register Address: DMA1 9000 0014 / 0034 / 0054 / 0074 / 0094 / 00B4 / 00D4 / 00F4 / 0114 / 0134 /...
Page 541 Register bit assignment Bits Access Mnemonic RW1TC NCIP RW1TC ECIP RW1TC NRIP Table 314: DMA Status/Interrupt Enable register bit definition B B u s D M A C o n t r o l l e r Reset Description Normal completion interrupt pending Set when a buffer descriptor is closed (for normal conditions).
Page 542 D M A C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access RW1TC D26:25 D15:00 Table 314: DMA Status/Interrupt Enable register bit definition 5 1 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 543 B B u s D M A C o n t r o l l e r 5 1 9 w w w . d i g i e m b e d d e d . c o m...
Page 545 BBus Utility he BBus utility provides chip-level support for the low speed peripherals in the NS9750 ASIC that reside on the Digi proprietary BBus. The BBus utility handles functions such as bus monitors, GPIO control, and peripheral reset. 5 2 1...
Page 546: Bbus Utility Control And Status Registers
B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s BBus Utility Control and Status registers The BBus Utility configuration registers are located at base address Table 315 lists the control and status registers in the BBus Utility.
Page 547: Master Reset Register
Master Reset register Address: 9060 0000 The Master Reset register contains the reset control signals for all BBus peripherals. All BBus peripherals, except the bridge, are held in reset after power-on reset is deasserted. All reset bits in this register are active high. Not used Register bit assignment Bits...
Page 548: Gpio Configuration Registers
GPIO Configuration registers #1 – #7 contain the configuration information for each of the 50 GPIO pins in the NS9750. Each GPIO pin is defined to have up to four functions. Configure each pin for the appropriate function and direction, as shown in Table 324: "GPIO Configuration register options"...
Page 549 Bits Access Mnemonic D31:28 gpio47 D27:24 gpio46 D23:20 gpio45 D19:16 gpio44 D15:12 gpio43 D11:08 gpio42 D07:04 gpio41 D03:00 gpio40 Table 318: GPIO Configuration Register #6 GPIO Configuration Register #5 Address: 9060 0020 gpio39 gpio35 Bits Access Mnemonic D31:28 gpio39 D27:24 gpio38 D23:20 gpio37...
Page 550 B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s GPIO Configuration Register #4 Address: 9060 001C gpio31 gpio27...
Page 551 Bits Access Mnemonic D31:28 gpio23 D27:24 gpio22 D23:20 gpio21 D19:16 gpio20 D15:12 gpio19 D11:08 gpio18 D07:04 gpio17 D03:00 gpio16 Table 321: GPIO Configuration register #3 GPIO Configuration Register #2 Address: 9060 0014 gpio15 gpio11 Bits Access Mnemonic D31:28 gpio15 D27:24 gpio14 D23:20 gpio13...
Page 552 B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s GPIO Configuration Register #1 Address: 9060 0010 gpio7 gpio3...
Page 553: Gpio Control Registers
GPIO Control Registers #1 and #2 contain the control information for each of the 50 GPIO pins in the NS9750, as shown in Table 325 and Table 326. When a GPIO pin is configured as a GPIO output, the corresponding bit in GPIO Control Registers #1 and #2 is driven out the GPIO pin.
Page 554 B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access Table 325: GPIO Control Register #2 GPIO Control Register #1 Address: 9060 0030 gpio...
Page 555 Bits Access Mnemonic gpio31 gpio30 gpio29 gpio28 gpio27 gpio26 gpio25 gpio24 gpio23 gpio22 gpio21 gpio20 gpio19 gpio18 gpio17 gpio16 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 gpio7 gpio6 Table 326: GPIO Control Register #1 Reset Description gpio[31] control bit gpio[30] control bit gpio[29] control bit gpio[28] control bit...
Page 556: Gpio Status Registers
GPIO Status Registers #1 and #2 contain the status information for each of the 50 GPIO pins in the NS9750, as shown in Table 327 and Table 328. In all configurations, the value on the GPIO input pin is brought to the Status register and the CPU has read-only access to the register.
Page 557 Bits Access Mnemonic gpio48 gpio47 gpio46 gpio45 gpio44 gpio43 gpio42 gpio41 gpio40 gpio39 gpio38 gpio37 gpio36 gpio35 gpio34 gpio33 gpio32 Table 327: GPIO Status Register #2 GPIO Status Register #1 Address: 9060 0040 gpio gpio gpio gpio gpio gpio gpio gpio gpio gpio...
Page 558 B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s The reset values for all of the status bits are undefined because they Note: depend on the state of the GPIO pins to NS9750. Bits Access...
Page 559: Bbus Monitor Register
Bits Access Table 328: GPIO Status Register #1 BBus Monitor register Address: 9060 0050 Write 0 to this register. Mnemonic Reset Description gpio6 undefined gpio[6] status bit gpio5 undefined gpio[5] status bit gpio4 undefined gpio[4] status bit gpio3 undefined gpio[3] status bit gpio2 undefined gpio[2] status bit...
Page 560: Bbus Dma Interrupt Status Register
B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s BBus DMA Interrupt Status register Address: 9060 0060 The BBus DMA Interrupt Status register contains the interrupt status bits for the BBus DMA Controller.
Page 561: Bbus Dma Interrupt Enable Register
Bits Access Table 329: BBus DMA Interrupt Status register BBus DMA Interrupt Enable register Address: 9060 0064 The BBus DMA Interrupt Enable register allows you to enable or disable the BBus DMA interrupts on an individual basis. Writing a 1 enables the interrupt. BINT_ BINT_ BINT_...
Page 562: Usb Configuration Register
B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s Bits Access Table 330: BBus DMA Interrupt Enable register USB Configuration register Address: 9060 0070 The USB Configuration register contains power-on USB configuration information.
Page 563: Endian Configuration Register
Address: 9060 0080 The Endian Configuration register contains the endian control for the BBus peripherals and the AHB bus master. NS9750 can be configured such that some peripherals transfer data in direct mode and some peripherals transfer data in DMA mode.
Page 564 B B u s U t i l i t y C o n t r o l a n d S t a t u s r e g i s t e r s Not used Register bit assignment Bits Access D31:13...
Page 565: Arm Wake-Up Register
Bits Access Table 332: Endian Configuration register ARM Wake-up register Address: 9060 0090 The ARM Wake-up register contains the ARM wake-up word used only by Serial Controller Interface #1. This pattern, when found as the next entry in the receive FIFO, causes a wake-up signal to be asserted to the ARM.
Page 567 C Master/Slave Interface he I C master/slave interface provides an interface between the ARM CPU and the I C bus. The I C master/slave interface basically is a parallel-to-serial and serial-to-parallel converter. The parallel data received from the ARM CPU has to be converted to an appropriate serial form to be transmitted to an external component using the I Similarly, the serial data received from the I appropriate parallel form for the ARM CPU.
Page 568: Overview
O v e r v i e w Overview The I C module is designed to be a master and slave. The slave is active only when the module is being addressed during an I and access the I slave are mutually exclusive. Physical I C bus The physical I...
Page 569 C command interface The I C module converts parallel (8-bit) data to serial data and serial data to parallel data between the NS9750 and the I The primary interface register for transmitting data is the (write-only). The primary interface register for receiving data is the (read-only).
Page 570: Locked Interrupt Driven Mode
I 2 C c o m m a n d i n t e r f a c e Locked interrupt driven mode C operates in a locked interrupt driven mode, which means that each command issued must wait for an interrupt response before the next command can be issued (illustrated in "Flow charts,"...
Page 571: Bus Arbitration
Bus arbitration M_READ arbitration process when the I bus owner, the transaction goes through. If the module loses bus arbitration, an interrupt is generated to the host processor and the command must be M_ARBIT_LOST reissued. C registers All registers have 8-bit definitions, but must be accessed in pairs. For example, TX_DATA_REG are read simultaneously.
Page 572: Command Transmit Data Register
I 2 C r e g i s t e r s Command Transmit Data register Address: 9050 0000 The Command Transmit Data ( register for transmission of data between the NS9750 BBus and I is write only. PIPE DLEN...
Page 573: Status Receive Data Register
Status Receive Data register Address: 9050 0000 The Status Receive Data register ( register for receipt of data between the NS9750 BBus and I read only. BSTS SCMDL Register bit assignment Bits Access D31:16 D11:08 D07:00 Table 338: STATUS_REG and RX_DATA_REG...
Page 574: Master Address Register
I 2 C r e g i s t e r s Master Address register Address: 9050 0004 If using 7-bit addressing, the master device address field uses only bits D07:01; otherwise, all 10 bits are used. Reserved Register bit assignment Bits Access D10:01...
Page 575: Slave Address Register
Slave Address register Address: 9050 0008 If using 7-bit addressing, the slave device address field uses only bits D07:01; otherwise, bits 10:01 are used. Reserved Register bit assignment Bits Access D10:01 Table 340: Slave Address register (7-bit and 10-bit) Reserved Gnrl call addr...
Page 576: Configuration Register
I 2 C r e g i s t e r s Configuration register Address: 9050 000C The Configuration register controls the timing on the I controls the external interrupt indication, which can be disabled. The I C bus clock timing is programmable by the parameter for standard mode is as follows: C_bus_clock = clk / ((CLREF*2) + 4 + scl_delay) clk = cpu_clk/4...
Page 577: Interrupt Codes
Bits Access D12:09 D08:00 Table 341: Configuration register Interrupt Codes Interrupts are signaled in the appropriate interrupt code (see Table 342: "Master/slave interrupt codes" on page 553). The ARM CPU waits for an interrupt by polling the signal. An interrupt is cleared by reading the signal down (minimum one cycle if another interrupt is stored).
Page 578 I n t e r r u p t C o d e s Code Name M_NO_ACK M_TX_DATA M_RX_DATA M_CMD_ACK S_RX_ABORT S_CMD_REQ S_NO_ACK S_TX_DATA_1ST S_RX_DATA_1ST S_TX_DATA S_RX_DATA S_GCA Table 342: Master/slave interrupt codes 5 5 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Master/slave Description Master...
Page 579: Software Driver
Software driver The I C master software driver uses three commands only: to start a read sequence M_READ to start a write sequence M_WRITE to give up the I M_STOP If, during a read or write sequence, another ARM CPU, a restart is performed on the I a new slave device address in the MAster Address register before the command request.
Page 580: Master Module (Normal Mode, 16-Bit)
F l o w c h a r t s Flow charts Master module (normal mode, 16-bit) write cmd M_NOP 5 5 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e host idle write cmd write (optional)
Page 581: Slave Module (Normal Mode, 16-Bit)
Notes: Writing M_ADDR_REQ Read on a non-existing slave. Do not wait for the slave to perform a STATUS_REG Slave module (normal mode, 16-bit) S_RX_ABORT Note: STATUS_REG is not required if the device address is not changed. NO_ACK are read simultaneously. RX_DATA_REG wait irq read...
Page 583: Lcd Controller
LCD Controller he NS9750 LCD (Liquid Crystal Display) controller is a DMA master module that connects to the AHB bus. The LCD controller provides the signals required to interface directly to TFT and STN color and monochrome LCD panels. LCD controller timing diagrams can be found in the Timing chapter.
Page 584: Programmable Parameters
L C D f e a t u r e s LCD features The NS9750 LCD controller provides these features: Dual 64-deep, 32-bit wide FIFOs, for buffering incoming display data Support for color and monochrome single- and dual-panel for Super Twisted...
Page 585: Lcd Panel Resolution
Signal polarity, active high or low AC panel bias Panel clock frequency Bits-per-pixel Display type, STN mono/color or TFT STN 4- or 8-bit interface mode STN dual- or single-panel mode Little endian, big endian, or WinCE mode Interrupt generation event LCD panel resolution The LCD can be programmed to support a wide range of panel resolutions, including but not limited to:...
Page 586: Number Of Colors
L C D f e a t u r e s Number of colors The number of colors supported differs per panel type. TFT panels TFT panels support one or more of these color modes: 1 bpp, palettized, 2 colors selected from available colors 2 bpp, palettized, 4 colors selected from available colors 4 bpp, palettized, 16 colors selected from available colors 8 bpp, palettized, 256 colors selected from available colors...
Page 587: Lcd Power Up And Power Down Sequence Support
LCD panel (see Figure 85, "Power up and power down sequences," on page 564): is applied simultaneously to the NS9750 and panel display driver logic. The following signals are pulled up to V CLCP, CLFP, CLAC, CLD[23:0], After the LCD controller is configured, a 1 is written to the LcdEn bit in the LCDControl register.
Page 588: Lcd Controller Functional Overview
L C D c o n t r o l l e r f u n c t i o n a l o v e r v i e w CLLP, CLCP, CLFP CLAC, CLLE CLPOWER CLD[23:0] Figure 85: Power up and power down sequences LCD controller functional overview The LCD controller translates pixel-coded data into the required formats and timing to drive a variety of single and dual mono and color LCDs.
Page 589: Clocks
HCLK/2 HCLK/4 HCLK/8 lcdclk/2 Note: lcdclk is an external clock input to NS9750. A divided-by-2 version of this value is sent to the LCD controller. internally. The clock sent to the LCD panel ( CLCDCLK using the PCD (panel clock divisor) value in the...
Page 590: Signals And Interrupts
L C D c o n t r o l l e r f u n c t i o n a l o v e r v i e w Signals and interrupts The LCD controller provides a set of programmable display control signals, and generates individual interrupts for different conditions.
Page 591 Register/palette programming AHB slave interface AHB master DMA FIFO interface controller Upper Lower Frame buffer panel panel access FIFO FIFO Figure 86: LCD controller block diagram Timing controller Palette RAM external Upper half-word Pixel serializer Lower half-word Upper panel formatter Lower panel formatter TFT panel...
Page 592: Ahb Master And Slave Interfaces
A H B i n t e r f a c e AHB interface The AHB interface includes the AHB slave interface and the AHB master interface. AHB master and slave interfaces The AHB master interface transfers display data from memory to the LCD controller DMA FIFOs.
Page 593: Pixel Serializer
L C D C o n t r o l l e r Pixel serializer The pixel serializer block reads the 32-bit wide LCD data from DMA FIFO output port, and extracts 24, 16, 8, 4, 2, or 1 bpp, depending on the current mode of operation. The LCD controller supports big endian, little endian, and WinCE data formats.
Page 594 A H B i n t e r f a c e 31 30 15 14 Figure 87: LBLP, DMA FIFO output bits 31:16 15 14 15 14 Figure 88: LBLP, DMA FIFO output bits 15:0 5 7 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e DMA FIFO OUTPUT BITS DMA FIFO OUTPUT BITS...
Page 595 DMA FIFO OUTPUT BITS 31 30 15 14 Figure 89: BBBP, DMA FIFO output bits 31:16 DMA FIFO OUTPUT BITS 15 14 15 14 Figure 90: BBBP, DMA FIFO output bits 15:0 w w w . d i g i e m b e d d e d . c o m L C D C o n t r o l l e r 5 7 1...
Page 596 A H B i n t e r f a c e 31 30 15 14 Figure 91: LBBP, DMA FIFO output bits 31:16 15 14 15 14 Figure 92: LBBP, DMA FIFO output bits 15:0 5 7 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e DMA FIFO OUTPUT BITS DMA FIFO OUTPUT BITS...
Page 597: Ram Palette
RAM palette The palette RAM is a 256 x 16 bit dual port RAM, physically structured as 128 x 32 bit. This allows two entries to be written into the palette from a single word write access. The least significant bit of the serialized pixel data selects between upper and lower halves of the palette RAM.
Page 598: Grayscaler
A H B i n t e r f a c e In 16- and 24-bpp TFT mode, the palette is bypassed and the pixel serializer output is used as the TFT panel data. Grayscaler A unique grayscale algorithm drives mono and color STN panels. For mono displays, the algorithm provides 15 grayscales.
Page 599: Generating Interrupts
Generating interrupts The LCD controller has three individually masked interrupts and a single combined interrupt. The single combined interrupt is asserted if any of the combined interrupts are asserted and unmasked. External pad interface signals The external pad interface signals are brought out through GPIO. Signal name CLPOWER CLLP...
Page 600 A H B i n t e r f a c e Table 346 shows which mode of operation. The abbreviations used in the table are defined as follows: CUSTN = Color upper panel STN, dual and/or single panel – CLSTN = Color lower panel STN, dual –...
Page 601 GPIO pin & description CLD[7] AE8=LCD data bit 7 (O1) CLD[6] AD9=LCD data bit 6 (O1) CLD[5] AF8=LCD data bit 5 (O1) CLD[4] AE9=LCD data bit 4 (O1) CLD[3] AF9=LCD data bit 3 (O1) CLD[2] AD10=LCD data bit 2 (O1) CLD[1] AE10=LCD data bit 1 (O1) CLD[0]...
Page 602 A H B i n t e r f a c e External pin CLD[15] CLD[14] CLD[13] CLD[12] CLD[11] CLD[10] CLD[9] CLD[8] CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] CLD[0] Table 347: LCD TFT panel signal multiplexing This LCD TFT panel signal multiplexing table shows the RGB alignment to a 15-bit TFT with the intensity bit not used.
Page 603: Registers
If you want reduced resolution, the least significant color bits can be dropped, starting with Red[0], Green[0], and Blue[0]. Registers Table 349 lists the LCD controller registers. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed. Address A080 0000 A080 0004...
Page 604: Lcdtiming0
R e g i s t e r s LCDTiming0 Address: A080 0000 The LCDTiming0 register controls the horizontal axis panel, which includes: Horizontal synchronization pulse width (HSW) Horizontal front porch (HFP) period Horizontal back porch (HBP) period Pixels-per-line (PPL) Register bit assignment Bits Access...
Page 605 Bits Access Mnemonic D15:08 D07:02 D01:00 Reserved Table 350: LCDTiming0 register Horizontal timing restrictions DMA requests new data at the beginning of a horizontal display line. Some time must be allowed for the DMA transfer and for the data to propagate down the FIFO path in the LCD interface.
Page 606: Lcdtiming1
R e g i s t e r s LCDTiming1 Address: A080 0004 The LCDTiming1 register controls the vertical axis panel, which includes: Number of lines-per-panel (LPP) Vertical synchronization pulse width (VSW) Vertical front porch (VFP) period Vertical back porch (VBP period) Register bit assignment Bits Access...
Page 607: Lcdtiming2 Register
Bits Access D23:16 D15:10 D09:00 Table 352: LCDTiming1 register LCDTiming2 register Address: A080 0008 The LCDTiming2 register provides controls for the timing signals. Mnemonic Reset Description 0x00 Vertical front porch Number of inactive lines at the end of the frame, before vertical synchronization period.
Page 608 R e g i s t e r s Reserved Rsvd Register bit assignment Bits Access D31:27 D25:16 Table 353: LCDTiming2 register 5 8 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 609 Data changes on the falling edge of Controls the phasing of the LCD data relative to the LCD clock ( ). The NS9750 changes the data on CLCP the opposite edge of the clock used to capture the data. Invert horizontal synchronization...
Page 610 R e g i s t e r s Bits Access D04:00 Table 353: LCDTiming2 register Panel clock divider restrictions The data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode: Dual panel color mode: Single panel mono 4-bit interface mode:...
Page 611: Lcdtiming3
LCDTiming3 Address: A080 000C LCDTiming3 controls whether the line-end signal, positive pulse, four delay from the last pixel of each display line. If the line-end signal is disabled, it is held permanently low. Register bit assignment Bits Access D31:17 D15:07 D06:00 Table 354: LCDTiming3 register LCDUPBASE and LCDLPBASE...
Page 612 R e g i s t e r s LCDUPBASE is used for these displays: Single panel STN Upper panel of dual panel STN LCDLPBASE is used for the lower panel of dual panel STN displays. You must initialize LCDUPBASE (and LCDLPBASE for dual panels) before Important: enabling the LCD controller.
Page 613: Lcdintrenable
Register bit assignment Bits Access D31:02 D01:00 Table 356: LCDLPBASE register LCDINTRENABLE Address: A080 0018 LCDINTRENABLE is the interrupt enable register. Setting bits within this register enables the corresponding raw interrupt LCDStatus bits to cause an interrupt to the system. LCDLPBASE LCDLPBASE Mnemonic...
Page 614: Lcdcontrol Register
R e g i s t e r s Register bit assignment Bits Access D31:05 D01:00 Table 357: LCDINTRENABLE register LCDControl register Address: A080 001C The LCDControl register controls the mode in which the LCD controller operates. Reserved LcdVComp Register bit assignment Bits Access D31:17...
Page 615 Bits Access Mnemonic WATERMARK D15:14 Reserved D13:12 LcdVComp LcdPwr BEPO BEBO Table 358: LCDControl register Reset Description LCD DMA FIFO watermark level LCD controller requests AHB bus when either of the DMA FIFOs have at least four empty locations. LCD controller requests AHB bus when either of the DMA FIFOs have at least eight empty locations.
Page 616 R e g i s t e r s Bits Access D03:01 Table 358: LCDControl register 5 9 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 617: Lcdstatus Register
LCDStatus register Address: A080 0020 The LCDStatus register provides raw interrupt status. On a read, the register returns three bits that can generate interrupts when set. On writes to the register, a bit value of 1 clears the interrupt corresponding to that bit.
Page 618: Lcdinterrupt Register
R e g i s t e r s LCDInterrupt register Address: A080 0024 The LCDInterrupt register is a bit-by-bit logical AND of the LCDStatus register and the LCDINTRENABLE register. Interrupt lines correspond to each interrupt. A logical OR of all interrupts is provided to the system interrupt controller.
Page 619: Lcdpalette Register
Register bit assignment Bits Access D31:00 Table 361: LCDUPCURR register Register bit assignment Bits Access D31:00 Table 362: LCDLPCURR register LCDPalette register Address A080 0200 – 03FC LCDPalette registers contain 256 palette entries organized as 128 locations of two entries per word. Only TFT displays use all of the palette entry bits.
Page 620 R e g i s t e r s Each word location contains two palette entries, which means that 128 word locations are used for the palette. When configured for little endian byte ordering, bits [15:00] are the lower- numbered palette entry and bits [31:16] are the higher-numbered palette entry.
Page 621 Bits Access Mnemonic D20:16 R[4:0] Int1 D14:10 B[4:0] D09:05 G[4:0] D04:00 R[4:0] Table 363: LCDPalette register Reset Description Red palette data For STN color displays, only the four most significant bits (04:01) are used. Used for monochrome displays. Intensity bit Can be used as the least significant bit of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different...
Page 622: Mberrorintr — Master Bus Error Interrupt
I n t e r r u p t s Interrupts The LCD controller drives a single interrupt back to the system, from four interrupt sources. Each of the three individual maskable interrupt sources is enabled or disabled by changing the mask bits in the LCDINTRENABLE register. The status of the individual interrupt sources can be read from the LCDStatus register.
Page 623: Lbuintr — Next Base Address Update Interrupt
L C D C o n t r o l l e r LBUINTR — Next base address update interrupt The LCD next base address update interrupt is asserted when either the LCDUPBASE or LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR incrementers (respectively).
Page 624 I n t e r r u p t s 6 0 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 625 Serial Control Module: UART he NS9750 ASIC supports four independent universal asynchronous/synchronous receiver/transmitter channels. Each channel supports several modes, conditions, and formats. 6 0 1...
Page 626: Features
F e a t u r e s Features Each channel supports these features: DMA transfers to and from system memory Independent programmable bit-rate generator High speed data transfer: 1.8432 Mbps (asynchronous) 32-byte TX FIFO 32-Byte RX FIFO Programmable data formats 5 to 8 data bits –...
Page 627: Bit-Rate Generator
Figure 93 shows the structure of the serial module. Bit Rate Generator Config Figure 93: Serial Module structure Bit-rate generator Each serial channel supports an independent programmable bit-rate generator. The bit-rate generator runs both the transmitter and receiver of a given channel (there is no split speed support).
Page 628: Uart Mode
U A R T m o d e Name X1_SYS_OSC/M BCLK ExtRxClk ExtTxClk Table 364: Bit-rate generation clock sources UART mode Many applications require a simple mechanism for sending low-speed information between two pieces of equipment. The universal asynchronous/synchronous receiver/transmitter (UART) protocol is the de facto standard for simple serial communications.
Page 629: Fifo Management
receiver waits for the start bit. When it finds the high-to-low transition, the receiver counts 8 sample times and uses this point as the bit-center for all remaining bits in the UART frame. Each bit-time is 16 clock ticks apart. When the UART is not transmitting data, it transmits a continuous stream of ones —...
Page 630: Receive Fifo Interface
F I F O m a n a g e m e n t When the system is configured to operate in little endian mode, the least significant bytes in the word written to the FIFO are transmitted first. For example, the long word transmitted first, and Processor interrupts vs.
Page 631 When the system is configured to operate in little endian mode, the least significant bytes in the word written to the FIFO are read first. For example, the long word first, and being read last. 0x11 When reading from the receive FIFO, the processor must perform a long word read operation.
Page 632: Serial Port Performance
The performance is limited by the speed of the SYSCLK operating the NS9750 ASIC. The configured speed for the internal PLL defines the BCLK rate; for UART (x8), the serial port maximum rate is 1834200 baud, for UART (x16), the serial port maximum rate is 921600 baud, and for UART (x32), the serial port maximum rate is 460800 baud.
Page 633 Address Description 9020 0008 Channel B Status Register A 9020 000C Channel B Bit-Rate register 9020 0010 Channel B FIFO Data register 9020 0014 Channel B Receive Buffer Gap Timer 9020 0018 Channel B Receive Character Gap Timer 9020 001C Channel B Receive Match register 9020 0020 Channel B Receive Match Mask register...
Page 634 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s The configuration registers for serial controller C are located at configuration registers for serial controller D are located at shows a single, two-channel address map for serial controllers C and D.
Page 635: Serial Channel B/A/C/D Control Register A
Serial Channel B/A/C/D Control Register A Address: 9020 0000 / 0040 9030 0000 / 0040 There are two Serial Channel B/A/C/D Control Registers A within each two-channel serial controller module. STICK Not used Register bit assignment Bits Access Table 367: Serial Channel B/A/C/D Control Register A STOP CTSTX RTSRX Mnemonic...
Page 636 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access D25:24 Table 367: Serial Channel B/A/C/D Control Register A 6 1 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 637 Bits Access Mnemonic D19:18 Not used D15:12 Not used D11:09 Table 367: Serial Channel B/A/C/D Control Register A S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Remote loopback...
Page 638: Serial Channel B/A/C/D Control Register B
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access D07:05 D04:01 Table 367: Serial Channel B/A/C/D Control Register A Serial Channel B/A/C/D Control Register B Address: 9020 0004 / 0044 9030 0004 / 0044...
Page 639 RBGT RCGT RTSTX Not used S e r i a l C o n t r o l M o d u l e : U A R T Not used MODE Reserved used w w w . d i g i e m b e d d e d . c o m Not used ORDR Reserved...
Page 640 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Register bit assignment Bits Access D31:28 D25:22 D21:20...
Page 641: Serial Channel B/A/C/D Status Register A
Bits Access D18:16 D14:12 D11:06 D04:00 Table 368: Serial Channel B/A/C/D Control Register B Serial Channel B/A/C/D Status Register A Address: 9020 0008 / 0048 9030 0008 / 0048 The fields in Serial Channel B/A/C/D Status Register A operate differently when DMA mode is used.
Page 642 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Match RBRK Bits Access D31:28 Table 369: Serial Channel B/A/C/D Status Register A 6 1 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 643 Bits Access Mnemonic CGAP 25:22 Not used D21:20 RXFDB Table 369: Serial Channel B/A/C/D Status Register A S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Character GAP timer...
Page 644 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access Table 369: Serial Channel B/A/C/D Status Register A 6 2 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 645 Bits Access Mnemonic ROVER RRDY Table 369: Serial Channel B/A/C/D Status Register A S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Receive overrun Indicates that a receive overrun error condition has been found.
Page 646 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access RW1TC Table 369: Serial Channel B/A/C/D Status Register A 6 2 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 647 Bits Access Mnemonic DSRI CTSI TRDY THALF Not used TEMPTY Table 369: Serial Channel B/A/C/D Status Register A S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Change in DSR...
Page 648: Serial Channel B/A/C/D Bit-Rate Register
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Serial Channel B/A/C/D Bit-rate register Address: 9020 000C / 004C 9030 000C / 004C The Serial Channel B/A/C/D Bit-rate register contains the serial channel timing...
Page 649 Bits Access Mnemonic TXSRC RXEXT TXEXT Table 370: Serial Channel B/A/C/D Bit-rate register S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Transmit clock source Internal External (input using GPIO pin) Controls the source of the transmitter clock.
Page 650 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access D25:24 Table 370: Serial Channel B/A/C/D Bit-rate register 6 2 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 651 Bits Access Mnemonic D20:19 TDCR D18:17 RDCR Not used Not used D14:00 Table 370: Serial Channel B/A/C/D Bit-rate register The next tables show sample UART baud rates. These rates can be produced using the recommended PLL reference oscillator frequency of 29.4912 MHz and setting the CLKMUX field in the Bit Rate register to 0.
Page 652 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Baud rate 1200 2400 4800 7200 9600 14400...
Page 653: Serial Channel B/A/C/D Fifo Data Register
Baud rate 1200 2400 4800 7200 9600 14400 19200 28800 38400 57600 115200 230400 460800 921600 1843200 Table 372: Bit-rate examples for X1_SYS_OSC/4 Serial Channel B/A/C/D FIFO Data register Address: 9020 0010 / 0050 9030 0010 / 0050 The Serial Channel B/A/C/D FIFO Data registers manually interface with the serial controller FIFOs instead of using DMA support.
Page 654: Serial Channel B/A/C/D Receive Buffer Gap Timer
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Reading from the receive register empties the receive FIFO. Data is available when the RRDY bit is set in Serial Channel Status Register A.
Page 655 Register bit assignment Bits Access Mnemonic TRUN D30:16 Not used D15:00 Table 374: Serial Channel B/A/C/D Receive Buffer GAP Timer S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Buffer GAP timer enable...
Page 656: Serial Channel B/A/C/D Receive Character Gap Timer
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Serial Channel B/A/C/D Receive Character GAP Timer Address: 9020 0018 / 0058 9030 0018 / 0058 The receive character GAP timer closes out a receive serial data buffer due to a gap...
Page 657 Bits Access Mnemonic D19:00 Table 375: Serial Channel B/A/C/D Receive Character GAP Timer S e r i a l C o n t r o l M o d u l e : U A R T Reset Description 0x00000 Character GAP timer Defines the required value for the receive character GAP timer.
Page 658: Serial Channel B/A/C/D Receive Match Register
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Serial Channel B/A/C/D Receive Match register Address: 9020 001C / 005C 9030 001C / 005C The Serial Channel B/A/C/D Receive Match register contains the four receive data...
Page 659: Serial Channel B/A/C/D Receive Match Mask Register
Serial Channel B/A/C/D Receive Match MASK register Address: 9020 0020 / 0060 9030 0020 / 0060 The Serial Channel B/A/C/D Receive Match MASK register contains the four receive match mask bytes that specify which bits in the Receive Match Data register should not be included in the match comparison.
Page 660: Serial Channel B/A/C/D Flow Control Register
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Serial Channel B/A/C/D Flow Control register Address: 9020 0034 / 0074 9030 0034 / 0074 The Serial Channel B/A/C/D Flow Control register allows you to define the flow...
Page 661 Bits Access Mnemonic D05:04 FLOW3 D03:02 FLOW2 D01:00 FLOW1 Table 378: Serial Channel B/A/C/D Flow Control register S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Flow control enable...
Page 662: Serial Channel B/A/C/D Flow Control Force Register
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Serial Channel B/A/C/D Flow Control Force register Address: 9020 0038 / 0078 9030 0038 / 0078 The Serial Channel B/A/C/D Flow Control Force register allows you to override the...
Page 663 Bits Access Mnemonic FORCE_EN D15:08 Not used D07:00 FORCE_ CHAR Table 379: Serial Channel B/A/C/D Flow Control Force register S e r i a l C o n t r o l M o d u l e : U A R T Reset Description Force transmit...
Page 664 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s 6 4 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 665 S e r i a l C o n t r o l M o d u l e : U A R T 6 4 1 w w w . d i g i e m b e d d e d . c o m...
Page 667 Serial Control Module: SPI he NS9750 ASIC supports four independent universal asynchronous/synchronous receiver/transmitter channels. Each channel supports several modes, conditions, and formats. 6 4 3...
Page 668: Features
F e a t u r e s Features Each channel supports these features: DMA transfers to and from system memory Independent programmable bit-rate generator High speed data transfer (synchronous) SPI master: 8.33 Mbps – SPI slave: 6.25 Mbps – 32-byte TX FIFO 32-Byte RX FIFO Figure 94 shows the structure of the serial module.
Page 669: Bit-Rate Generator
Bit-rate generator Each serial channel supports an independent programmable bit-rate generator. The bit-rate generator runs both the transmitter and receiver of a given channel (there is no split speed support). You can configure the bit-rate generator to use external clock input or internal system timing as its timing reference.
Page 670: Spi Mode
S P I m o d e SPI mode The NS9750 ASIC SPI controller provides these key features: Four-wire interface ( Master or slave configuration Programmable MSB/LSB formatting Programmable Programmable SPI mode (0, 1, 2, 3) The SPI controller provides a full-duplex, synchronous, character-oriented data...
Page 671: Transmit Fifo Interface
Serial channel B/A/C/D bit rate register settings mode SPCPOL Table 381: SPI mode definitions FIFO management Data flow between a serial controller and memory occurs through the FIFO blocks within each serial controller module. Each serial controller provides both a 32-byte transmit FIFO and a 32-byte receive FIFO.
Page 672: Receive Fifo Interface
F I F O m a n a g e m e n t Processor interrupts vs. DMA The transmit FIFO can be filled using processor interrupts or the DMA controller. Using processor interrupts The processor can write one long word (4 bytes) of data to the transmit FIFO when the TRDY field in Serial Channel B/A/C/D Status Register A (see "Serial Channel B/A/ C/D Status Register A,"...
Page 673 When reading from the receive FIFO, the processor must perform a long word read operation. Each time a read cycle to the receive FIFO is performed, the receive FIFO advances to the next long word entry. The processor cannot read individual bytes from the same FIFO long word entry.
Page 674: Serial Port Control And Status Registers
The serial ports have a finite performance limit on their ability to handle various serial protocols. The performance is limited by the speed of the SYSCLK operating the NS9750 ASIC. The configured speed for the internal PLL defines the BCLK rate; for SPI, the serial port maximum rate is...
Page 675 Address Description 9020 0044 Channel A Control Register B 9020 0048 Channel A Status Register A 9020 004C Channel A Bit-Rate register 9020 0050 Channel A FIFO Data register Table 382: Serial channel B & A configuration registers The configuration registers for serial controller C are located at configuration registers for serial controller D are located at shows a single, two-channel address map for serial controllers C and D.
Page 676: Serial Channel B/A/C/D Control Register A
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Serial Channel B/A/C/D Control Register A Address: 9020 0000 / 0040 9030 0000 / 0040 There are two Serial Channel B/A/C/D Control Registers A within each two-channel...
Page 677 Bits Access Mnemonic D19:12 Not used D11:09 ERXDMA D07:05 Reserved D04:01 Table 384: Serial Channel B/A/C/D Control Register A S e r i a l C o n t r o l M o d u l e : S P I Reset Description Local loopback...
Page 678 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access Mnemonic Reset Description ETXDMA Enable transmit DMA Enables the transmitter to interact with a DMA channel.
Page 679: Serial Channel B/A/C/D Control Register B
Serial Channel B/A/C/D Control Register B Address: 9020 0004 / 0044 9030 0004 / 0044 There are two Serial Channel B/A/C/D Control Registers B within each two-channel serial controller module. The CE field in Serial Channel Control register A should not be set until Note: these control bits are stabilized.
Page 680 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access D21:20 D18:12 D11:06 D04:00 Table 385: Serial Channel B/A/C/D Control Register B 6 5 6...
Page 681: Serial Channel B/A/C/D Status Register A
Serial Channel B/A/C/D Status Register A Address: 9020 0008 / 0048 9030 0008 / 0048 The fields in Serial Channel B/A/C/D Status Register A operate differently when DMA mode is used. Many fields are not required for DMA mode, as they are copied to the status field in the DMA buffer descriptor.
Page 682 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access Table 386: Serial Channel B/A/C/D Status Register A 6 5 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 683 Bits Access Mnemonic RHALF D07:04 Not used TRDY Table 386: Serial Channel B/A/C/D Status Register A S e r i a l C o n t r o l M o d u l e : S P I Reset Description Receive FIFO half full Indicates that the receive data FIFO contains at least 20...
Page 684: Serial Channel B/A/C/D Bit-Rate Register
S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access Table 386: Serial Channel B/A/C/D Status Register A Serial Channel B/A/C/D Bit-rate register Address: 9020 000C / 004C 9030 000C / 004C...
Page 685 Register bit assignment Bits Access Mnemonic EBIT TMODE RXSRC TXSRC RXEXT Table 387: Serial Channel B/A/C/D Bit-rate register S e r i a l C o n t r o l M o d u l e : S P I Reset Description Bit-rate generator enable...
Page 686 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access D25:24 Table 387: Serial Channel B/A/C/D Bit-rate register 6 6 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 687 Bits Access Mnemonic RXCINV SPCPOL D20:19 TDCR Table 387: Serial Channel B/A/C/D Bit-rate register S e r i a l C o n t r o l M o d u l e : S P I Reset Description Receive clock invert Controls the relationship between receive clock and receive data: When set to 0, the receive data input is sampled at...
Page 688 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s Bits Access D18:17 Table 387: Serial Channel B/A/C/D Bit-rate register 6 6 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic...
Page 689: Serial Channel B/A/C/D Fifo Data Register
Bits Access D14:00 Table 387: Serial Channel B/A/C/D Bit-rate register Serial Channel B/A/C/D FIFO Data register Address: 9020 0010 / 0050 9030 0010 / 0050 The Serial Channel B/A/C/D FIFO Data registers manually interface with the serial controller FIFOs instead of using DMA support. Writing to the transmit register loads the transmit FIFO.
Page 690 S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s the Serial Channel FIFO Data register automatically clears the RRDY bit in Serial Channel Status Register A.
Page 691 S e r i a l C o n t r o l M o d u l e : S P I 6 6 7 w w w . d i g i e m b e d d e d . c o m...
Page 693 IEEE 1284 Peripheral Controller he IEEE 1284 peripheral port supports compatibility mode, nibble mode, byte mode, and ECP mode of operations as a peripheral device. The IEEE 1284 port does not support EPP/mode daisy chain or multiplexer operations. 6 6 9...
Page 694: Requirements
R e q u i r e m e n t s Requirements Two components are required to run the IEEE 1284 peripheral-to-host interface: Clock divider. Required to generate the 1284-port operating clock from the BBus clock. The operating range of the port clock typically is 100 KHz–2 MHz.
Page 695: Compatibility Mode
Traffic direction in the IEEE 1284 is classified as either forward or reverse. Note: The forward direction is equivalent to NS9750 receive. Similarly, the reverse direction is equivalent to NS9750 transmit. Compatibility mode Compatibility mode is the standard parallel port (SPP) forward transmission mode (from the host), also known as the Centronics mode.
Page 696: Nibble Mode
O v e r v i e w Nibble mode Nibble mode can send a byte of information to the host by sending two nibbles. This mode operates only in reverse mode. Figure 97 shows the timing relationship on the port interface. Figure 97: Nibble mode data transfer cycles Byte mode Byte mode sends information to the host over the data lines, at 8 bits per cycle.
Page 697: Ecp Mode
Run_Length_Encoding (RLE) data compression enables real time data compression that can achieve ratios up to 64:1. NS9750 uses RLE decoding to enable large raster images with large strings of identical data to be transferred to system memory.
Page 698 O v e r v i e w Figure 99: ECP mode forward transfer cycles Host processing sequence example: The host puts the data on the data lines and indicates a data cycle by setting high. HostAck The host asserts The peripheral acknowledges the host by setting The host sets peripheral.
Page 699: Data And Command Fifos
For normal operation, it is recommended that you configure this 1284 interface for DMA control. DMA provides a faster and more efficient interface between IEEE 1284 and the rest of the NS9750. CPU mode is more suitable for diagnostic and testing purposes.
Page 700: Ieee 1284 Negotiation
O v e r v i e w Because the NS9750 functions only as a slave, it is not necessary to provide the capability of driving any non-IEEE 1284 compliant commands back to the host. The 1284 commands are not designed to be stored and passed along. To...
Page 701: Bbus Slave And Dma Interface Register Map
0000 0000 Table 389: Extensibility byte values The NS9750 directly supports RLE compression. The device ID can be returned in any supported reverse channel mode. The device ID is a length field followed by a string of ASCII characters that define the peripheral’s characters and/or capabilities.
Page 702 B B u s s l a v e a n d D M A i n t e r f a c e Address 9040 0008 9040 000C 9040 0010 9040 0014 – 9040 0018 9040 001C 9040 0020 9040 0024 9040 0028 9040 0100 –...
Page 703: Ieee 1284 General Configuration Register
Address 9040 016C – 9040 0170 9040 0174 9040 0178 Table 390: 1284 Control and Status registers IEEE 1284 General Configuration register Address: 9040 0000 The IEEE 1284 General Configuration register contains miscellaneous control settings for the IEEE 1284 module. Rsvd AFSH Register bit assignment...
Page 704 B B u s s l a v e a n d D M A i n t e r f a c e Bits Access D11:10 D:09:08 D07:06 D05:04 Table 391: IEEE 1284 General Configuration register 6 8 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset...
Page 705: Interrupt Status And Control Register
Bits Access Table 391: IEEE 1284 General Configuration register Interrupt Status and Control register Address: 9040 0004 The Interrupt Status and Control register contains miscellaneous control settings for the IEEE 1284 module. Bits with an access type of R/C (read/clear) can be set only by hardware, and are cleared by software by writing a 1 to the corresponding bit location.
Page 706 B B u s s l a v e a n d D M A i n t e r f a c e Bits Access D16:11 Table 392: Interrupt Status and Control register 6 8 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 707 Bits Access Mnemonic FDFBG FCFBG FDFMB FCFMB FDFRI FCFRI PC1I Reserved Table 392: Interrupt Status and Control register I E E E 1 2 8 4 P e r i p h e r a l C o n t r o l l e r Reset Description Forward data FIFO byte gap...
Page 708: Fifo Status Register
B B u s s l a v e a n d D M A i n t e r f a c e FIFO Status register Address: 9040 0008 The FIFO Status register allows the CPU to determine that status of all FIFOs in the 1284 module.
Page 709 Bits Access Mnemonic FCFR D10:08 Reserved D07:06 FDFDR FDFE FDFAE FDFR Table 393: FIFO Status register I E E E 1 2 8 4 P e r i p h e r a l C o n t r o l l e r Reset Description Forward command FIFO ready...
Page 710: Forward Command Fifo Read Register
B B u s s l a v e a n d D M A i n t e r f a c e Bits Access Table 393: FIFO Status register Forward Command FIFO Read register Address: 9040 000C Register bit assignment Bits Access D31:00...
Page 711: Forward Data Fifo Read Register
Forward Data FIFO Read register Address: 9040 0010 Register bit assignment Bits Access D31:00 Table 395: Forward Data FIFO Read register Reverse FIFO Write register/Reverse FIFO Write Register — Last Address: 9040 001C / 9040 0020 Both registers are 32 bits. FwDatFifoReadReg FwDatFifoReadReg Mnemonic...
Page 712 B B u s s l a v e a n d D M A i n t e r f a c e Register bit assignment Bits Access D31:00 D31:00 Table 396: Reverse Data FIFO Write register/Reverse Data FIFO Write Register — Last 6 8 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e RvFifoWriteReg - Last...
Page 713: Forward Command Dma Control Register
Forward Command DMA Control register Address: 9040 0024 The Forward Command DMA Control register controls when the Forward command DMA buffer is closed, using two components: 16-bit maximum buffer counter. The maximum buffer counter increments each time a DMA transfer occurs, by the number of bytes in the transfer. The counter is reset each time a DMA is completed.
Page 714: Forward Data Dma Control Register
B B u s s l a v e a n d D M A i n t e r f a c e Register bit assignment Bits Access D31:16 D15:00 Table 397: Forward Command DMA Control register Forward Data DMA Control register Address: 9040 0028 The Forward Data DMA Control register controls when the forward data DMA buffer is closed, using two components:...
Page 715: Printer Data Pins Register
Forward data FIFO ready, which normally means the threshold has been met, is asserted. This results in continuation of the currently active DMA until the FIFO is empty. When the data in the FIFO, including the incomplete dwords in Step 1, is output through DMA, the DMA is terminated.
Page 716: Port Status Register, Host
B B u s s l a v e a n d D M A i n t e r f a c e Register bit assignment Bits Access D31:08 D07:00 Table 399: pd — Printer Data Pins register Port Status register, host Address: 9040 0104 Register bit assignment Bits...
Page 717: Port Control Register
Port Control register Address: 9040 0108 The Port Control register can control IEEE 1284 pins only if no modes are Note: enabled in the Master Enable register (see"Master Enable register" on page 697). Register bit assignment Bits Access D31:08 D02:00 Table 401: pcr —...
Page 718: Port Status Register, Peripheral
B B u s s l a v e a n d D M A i n t e r f a c e Port Status register, peripheral Address: 9040 010C Bits Access D31:08 D02:00 Table 402: pin — Port Status register, peripheral Feature Control Register A Address: 9040 0114 Feature Control Register A enables buffer trigger levels for printer port operations.
Page 719: Feature Control Register B
Register bit assignment Bits Access D31:01 Table 403: fea — Feature Control Register A Feature Control Register B Address: 9040 0118 You must set bit[0] to 1 in Feature Control Register B. Bits[31:01] are reserved. Interrupt Enable register Address: 9040 011C The Interrupt Enable register enables interrupts to be generated on certain conditions.
Page 720 B B u s s l a v e a n d D M A i n t e r f a c e Bits Access D03:02 Table 404: fei — Interrupt Enable register 6 9 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 721: Master Enable Register
Master Enable register Address: 9040 0120 The Master Enable register enables different IEEE 1284 modes and automatic transfer modes. Set both AutoTransfer and AutoNegotiate to enable hardware to control Note: the 1284 peripheral interface signals. Register bit assignment Bits Access D31:07 D01:00 Table 405: fem —...
Page 722: Extensibility Byte Requested By Host
B B u s s l a v e a n d D M A i n t e r f a c e Extensibility Byte Requested by Host Address: 9040 0124 This register is updated shortly after a new negotiation occurs (event 4 of the negotiation process;...
Page 723: Interrupt Status Register
Register bit assignment Bits Access D31:08 D05:00 Table 407: ecr — Extended Control register Interrupt Status register Address: 9040 012C Interrupts are cleared when this register is read. These interrupts are needed by software no matter which mode (DMA or CPU) is being used. Register bit assignment Bits Access...
Page 724: Pin Interrupt Mask Register
B B u s s l a v e a n d D M A i n t e r f a c e Bits Access Table 408: sti — Interrupt Status register Pin Interrupt Mask register Address: 9040 0134 The Pin Interrupt Mask register enables IEEE 1284 pin interrupts.
Page 725: Pin Interrupt Control Register
Pin Interrupt Control register Address: 9040 0138 The Pin Interrupt Control register configures IEEE 1284 pin interrupt edge levels. Register bit assignment Bits Access D31:04 Table 410: pit — Pin Interrupt Control register Reserved Reserved Mnemonic Reset Reserved n_autofd edge n_init edge n_slctin edge n_strobe edge...
Page 726: Granularity Count Register
B B u s s l a v e a n d D M A i n t e r f a c e Granularity Count register Address: 9040 0168 The Granularity Count register controls the value of the granularity counter for automatic processing modes.
Page 727: Forward Address Register
Forward Address register Address: 9040 0174 The Forward Address register is updated when a channel address command is received during a forward ECP transfer. Register bit assignment Bits Access D31:08 D07:00 Table 412: eca — Forward Address register Reserved Reserved Mnemonic Reset Reserved...
Page 728: Core Phase (Ieee1284) Register
B B u s s l a v e a n d D M A i n t e r f a c e Core Phase (IEEE1284) register Address: 9040 0178 Register bit assignment Bits Access D31:08 D07:00 Table 413: Core Phase register 7 0 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Reserved...
Page 729 2,000ns at the beginning of data transfer. If the host does not support these states, however, the NS9750 will be unable to transmit data in nibble or byte mode. Note that there is no impact for a host that fully implements IEEE 1284.
Page 731 USB Controller Module SB 2.0 provides a standard “plug-and-play” interface for desktop communications at low to moderate speeds. The USB module in NS9750 supports both full-speed (12Mbps) and low-speed (1.5 Mbps) operation. 7 0 7...
Page 732: Usb Module Architecture
O v e r v i e w Overview USB consists of point-to-point connections between one host and any number of hubs and devices; the number of hubs and devices combined cannot exceed 127. Point-to- point connections are established between a downstream port and an upstream port, as shown: Host/hub/device Host...
Page 733 U S B C o n t r o l l e r M o d u l e BBus Config FIFOs and DMA channels Host block Device block XCVR Figure 101: USB module architecture The device block handles most packets that contain control and/or configuration information requiring device driver interaction to maintain only the DMA descriptor lists.
Page 734: Usb Device Block
U S B d e v i c e b l o c k given pipe has not been configured or updated, or otherwise is not ready to send or receive the required data, the device block issues The host block supports the Open Host Controller Interface (OHCI) interface model for USB communications.
Page 735: Packet And Data Flow
U S B C o n t r o l l e r M o d u l e Packet and data flow The device block responds to packets initiated by the host. There are 16 DMA channels in this block. DMA channels 1 and 2 move data to and from system memory for control transfers for logical endpoint 0.
Page 736: Logical And Physical Endpoints
H o s t b l o c k Logical and physical endpoints Each alternate of each interface of each configuration can use as many as 16 logical endpoints. Physical endpoints in the device block are programmable by software for configuration/interface/alternate number.
Page 737: Packet Data Flow
Slave IF Master IF BBUS Figure 103: USB host architecture Packet data flow The host block initiates all transfers on the USB. Data travels through a four-word FIFO in either direction. The Serial Interface Engine (SIE) performs the tasks required to receive and send packets on the USB.
Page 738: Usb Device Endpoint
U S B d e v i c e e n d p o i n t consumed. Burst transfers move a maximum of 8 bytes in long word transactions. FIFO content from more than one transfer descriptor is broken into separate memory operations.
Page 739: Handling Usb-In Packet Errors
Handling USB-IN packet errors USB-IN packet errors are sent from the USB device to the USB host. The USB host either responds with an ACK packet to indicate successful transmission or does not respond at all to indicate that there was an error in transmission. These are the steps that must be taken to retransmit the packet in error: Determine that the error has occurred through an interrupt.
Page 740: Usb Block Registers
U S B b l o c k r e g i s t e r s USB block registers The USB module configuration registers are located at base address 9010_0000. Table 415 provides the address register map for the USB “modules” within the USB block.
Page 741: Global Control And Status Register
Global Control and Status register Address: 9010 0000 The Global Control and Status register contains all USB global and status information. The USB can operate as a device or host, but cannot operate as both simultaneously unless used in feedback mode. Feedback mode is useful for development and testing only.
Page 742: Device Control And Status Register
(bit 0 in this register). When the NS9750 is in device mode, the device driver can write a 1 to this field to enable remote wakeup. When the NS9750 is in host mode, this field is ignored. Not used Always read as 1.
Page 743 Set to 1 by the device driver to initiate a resume sequence. This field is cleared to a 0 to end a resume sequence. Always read as 0. Self-powered (SELF_PWR) This field should always be written as 1, since the NS9750 is always self-powered. Always write to 1. SYNC_FRAME support Indicates whether the device block supports the packet.
Page 744: Global Interrupt Enable Register
U S B G l o b a l r e g i s t e r s Global Interrupt Enable register Address: 9010 000C The Global Interrupt Enable register contains the global interrupt enable information. All interrupts are enabled by writing a 1 and disabled by writing a 0. GLB_ Not used used...
Page 745: Global Interrupt Status Register
FIFO Interrupt Enable register. URST Generate an interrupt when the NS9750 is in device mode and receives an interrupt from the host. Generate an interrupt when the NS9750 is in device mode and receives an SOF (start of frame) packet.
Page 746 U S B G l o b a l r e g i s t e r s For diagnostics, each bit serviced here can also be set to 1 by writing a 1 when the bit is set to 0. The DMA interrupts must be serviced in the USB DMA device block.
Page 747 DMA channel 1 interrupt. Service in the USB DMA block. Bit-wise logical OR of the FIFO interrupt status fields. Asserted when the NS9750 is in device mode and receives an interrupt from the host. Asserted when the NS9750 is in device mode and receives an SOF (start of frame) packet.
Page 748: Device Ip Programming Control/Status Register
U S B G l o b a l r e g i s t e r s Bits Access RW1TC Table 420: Global Interrupt Status register Device IP Programming Control/Status register Address: 9010 0014 The Device IP Programming Control/Status register contains the USB device CSR dynamic programming control and status information.
Page 749: Usb Host Block Registers
USB host block registers The USB Host Block registers are for the host controller defined in the Open HCI specification for USB. All references to HC refer to the USB host block in the NS9750. Reserved bits The Host Controller Driver (HCD) should always preserve the value(s) of the reserved field.
Page 750: Hcrevision Register
U S B h o s t b l o c k r e g i s t e r s Address 9010 1008 9010 100C 9010 1010 9010 1014 9010 1018 9010 101C 9010 1020 9010 1024 9010 1028 9010 102C 9010 1030 9010 1034...
Page 751: Hccontrol Register
Register bit assignment Bits Access D31:08 D07:00 Table 423: HcRevision register HcControl register Address: 9010 1004 The HcControl register defines the operating modes for the host controller. Most of the fields in this register are modified only by the host controller driver, with the exception of the HostControllerFunctionalState and RemoteWakeupConnected fields.
Page 752 U S B h o s t b l o c k r e g i s t e r s Bits Access Table 424: HcControl register 7 2 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 753 Bits Access Mnemonic D07:06 HCFS Table 424: HcControl register U S B C o n t r o l l e r M o d u l e Reset Description HostControllerFunctionalState (b = binary) (initial state) USBRESET USBRESUME USBOPERATIONAL USBSUSPEND A transition to USBOPERATIONAL causes SOF generation to begin 1 ms later.
Page 754: Hccommandstatus Register
U S B h o s t b l o c k r e g i s t e r s Bits Access D01:00 Table 424: HcControl register HcCommandStatus register Address: 9010 1008 7 3 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 755 The host controller uses the HcCommandStatus register to receive commands issued by the host controller driver, as well as to reflect the current status of the host controller. The HcCommandStatus register appears to the host controller driver as a write to set register. The host controller must ensure that bits written as 1 become set in the register while bits written as 0 remain unchanged in the register.
Page 756 U S B h o s t b l o c k r e g i s t e r s Bits Access D15:04 Table 425: HcCommandStatus register 7 3 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 757: Hcinterruptstatus Register
Address: 9010 100C The HcInterruptStatus register provides status on various events that cause hardware interrupts. When an event occurs, the NS9750 sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see "HcInterruptEnable register,"...
Page 758 U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D29:07 Table 426: HcInterruptStatus register 7 3 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 759: Hcinterruptenable Register
Bits Access Table 426: HcInterruptStatus register HcInterruptEnable register Address: 9010 1010 Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterrupt Status register (see "HcInterruptStatus register," beginning on page 733). The HcInterruptEnable register controls which events generate a hardware interrupt.
Page 760 U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D29:07 Table 427: HcInterruptEnable register 7 3 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Reserved Reserved Mnemonic...
Page 761: Hcinterruptdisable Register
Bits Access Table 427: HcInterruptEnable register HcInterruptDisable register Address: 9010 1014 Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register (see "HcInterruptStatus register," beginning on page 733). The HcInterruptDisable register works in conjunction with the HcInterruptEnable register (see "HcInterruptEnable register,"...
Page 762 U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D29:07 Table 428: HcInterruptDisable register 7 3 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 763: Hchcca Register
Bits Access Table 428: HcInterruptDisable register HcHCCA register Address: 9010 1018 The HcHCCA register contains the physical address of the host controller communication area (HCCA), which is a RAM area with a defined format. The host controller driver determines the alignment restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA.
Page 764: Hcperiodcurrented Register
U S B h o s t b l o c k r e g i s t e r s HcPeriodCurrentED register Address: 9010 101C The HcPeriodCurrentED register contains the physical address of the current isochronous or interrupt endpoint descriptor. 7 4 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e PCED...
Page 765: Hccontrolheaded Register
Register bit assignment Bits Access D31:04 D03:00 Table 430: HcPeriodCurrentED HcControlHeadED register Address: 9010 1020 The HcHeadControlED register contains the physical address of the first endpoint descriptor of the control list. Mnemonic Reset Description PCED PeriodCurrentED Used by the host controller to point to the head of one of the periodic lists that will be processed in the current frame.
Page 766: Hccontrolcurrented Register
U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D31:04 D03:00 Table 431: HcControlHeadED register HcControlCurrentED register Address: 9010 1024 The HcControlCurrentED register contains the physical address of the control list’s current endpoint descriptor.
Page 767: Hcbulkheaded Register
Register bit assignment Bits Access D31:04 D03:00 Table 432: HcControlCurrentED register HcBulkHeadED register Address: 9010 1028 The HcBulkHeadED register contains the physical address of the first endpoint descriptor of the bulk list. Mnemonic Reset Description CCED ControlCurrentED This pointer is advanced to the next endpoint descriptor after serving the present one.
Page 768: Hcbulkcurrented Register
U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D31:04 D03:00 Table 433: HcBulkHeadED register HcBulkCurrentED register Address: 9010 102C The HcBulkCurrentED register contains the physical address of the bulk list’s current endpoint.
Page 769 Register bit assignment Bits Access Mnemonic D31:04 BCED D03:00 Not used Table 434: HcBulkCurrentED register U S B C o n t r o l l e r M o d u l e Reset Description BulkCurrentED BulkCurrentED is advanced to the next endpoint descriptor after the host controller has served the present endpoint descriptor.
Page 770: Hcdonehead Register
U S B h o s t b l o c k r e g i s t e r s HcDoneHead register Address: 9010 1030 The HcDoneHead register contains the physical address of the last completed transfer descriptor that was added to the Done queue. In normal operation, the host controller driver should not need to read this register as its content is written periodically to the host controller communication area.
Page 771: Hcfminterval Register
HcFmInterval register Address: 9010 1034 The HcFmInterval register contains the 14-bit value that indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the full speed maximum packet size that the host controller can transmit or receive without causing a scheduling overrun.
Page 772: Hcfmremaining Register
U S B h o s t b l o c k r e g i s t e r s Bits Access D13:00 Table 436: HcFmInterval register HcFmRemaining register Address: 9010 1038 The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame.
Page 773: Hcfmnumber Register
Register bit assignment Bits Access D30:14 D13:00 Table 437: HcFmRemaining register HcFmNumber register Address: 9010 103C The HcFmNumber register is a 16-bit counter that provides a timing reference among events happening in the host controller driver. The host controller driver can use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register.
Page 774: Hcperiodicstart Register
U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D31:16 D15:00 Table 438: HcFmNumber register HcPeriodicStart register Address: 9010 1040 Reserved Register bit assignment Bits Access D31:14...
Page 775: Hclsthreshold Register
Bits Access D13:00 Table 439: HcPeriodicStart register HcLsThreshold register Address: 9010 1044 The HcLSThreshold register contains a value used by the host controller to determine whether to commit to the transfer of a maximum-of-8-byte LS packet before EOF. Neither the host controller driver not the host controller is allowed to change this value.
Page 776: Root Hub Partition Registers
U S B h o s t b l o c k r e g i s t e r s Register bit assignment Bits Access D31:12 D11:00 Table 440: HcLsThreshold register Root hub partition registers The remaining USB host block registers are dedicated to the USB root hub, which is an integral part of the host controller although it is a functionally separate entity.
Page 777: Hcrhdescriptora Register
HcRhDescriptorA register Address: 9010 1048 The HcRhDescriptorA register is the first of two registers describing the characteristics of the root hub. The root hub is the logical hub built into a USB host. Reset values are implementation-specific. Reserved Register bit assignment Bits Access D31:24...
Page 778 U S B h o s t b l o c k r e g i s t e r s Bits Access D07:00 Table 441: HcRhDescriptorA register 7 5 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 779: Hcrhdescriptorb Register
HcRhDescriptorB register Address: 9010 104C The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation- specific. Register bit assignment Bits Access D31:16...
Page 780: Hcrhstatus Register
U S B h o s t b l o c k r e g i s t e r s Bits Access D15:00 Table 442: HcRhDesdcriptorB register HcRhStatus register Address: 9010 1050 The HcRhStatus register has two parts: The lower word of a Dword represents the hub status field. The upper word of the Dword represents the hub status change field.
Page 781 Bits Access Mnemonic CCIC LPSC DRWE D14:02 Not used Table 443: HcRhStatus register U S B C o n t r o l l e r M o d u l e Reset Description OverCurrentIndicatorChange Set by hardware when a change has occurred to the OCI field (bit 01 in this register).
Page 782 U S B h o s t b l o c k r e g i s t e r s Bits Access Mnemonic Reset Description LocalPowerStatus (read) Not supported; always read as 0. ClearGlobalPower (write) In global power mode (PowerSwitchingMode=0), this bit is always written to 1 to turn off power to all ports (clear PowerPortStatus).
Page 783: Hcrhportstatus[1] Register
HcRhPortStatus[1] register Address: 9010 1054 The HcRhPortStatus register controls and reports port events on a per-port basis. The lower word reflects port status; the upper word reflects the status change bits. If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes.
Page 784 U S B h o s t b l o c k r e g i s t e r s Bits Access D15:10 Table 444: HcRhPortStatus[1] register 7 6 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 785 Bits Access Mnemonic LSDA (cont) Table 444: HcRhPortStatus[1] register U S B C o n t r o l l e r M o d u l e Reset Description LowSpeedDeviceAttached (read) Full speed device attached Low speed device attached Indicates the speed of the device attached to this port.
Page 786 U S B h o s t b l o c k r e g i s t e r s Bits Access D07:05 Table 444: HcRhPortStatus[1] register 7 6 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Mnemonic Reset Description...
Page 787 Bits Access Mnemonic Table 444: HcRhPortStatus[1] register U S B C o n t r o l l e r M o d u l e Reset Description PortSuspendStatus (read) Port is not suspended Port is suspended Indicates that the port is suspended or in the resume sequence.
Page 788 Port is disabled Port is enabled Indicates whether the port is enabled or disabled. The NS9750 can clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error (such as babble) is found. This change also causes PortEnableStatusChange (bit 17 in this register) to be set.
Page 789: Usb Device Block Registers
USB Device Block registers Table 445 provides the addresses of the USB Device Block registers. Address 9010 2000 9010 2004 9010 2008 9010 200C 9010 2010 9010 2014 9010 2018 9010 201C 9010 2020 9010 2024 9010 2028 9010 202C 9010 2030 Table 445: USB Device Block registers address map Device Descriptor/Setup Command register...
Page 790: Endpoint Descriptor #0–#11 Registers
U S B D e v i c e B l o c k r e g i s t e r s Endpoint Descriptor #0–#11 registers Address: 9010 2004 / 2008 / 200C / 2010 / 2014 / 2018 / 201C / 2020 / 2024 / 2028 / 202C / 2030 The Endpoint Descriptor registers store the endpoint information.
Page 791: Usb Device Endpoint Fifo Control And Data Registers
Bits Access D03:00 Table 446: Endpoint Descriptor register (for endpoint descriptors 0–11) USB Device Endpoint FIFO Control and Data registers Table 447 provides the addresses for the endpoint registers found in the application logic that interfaces to the USB device block. Address 9010 3000 9010 3004...
Page 792 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s Address 9010 30A4 9010 30A8...
Page 793: Fifo Interrupt Status Registers
1 to the corresponding bit position. If the status generating condition is present after writing a 1, the appropriate status bit is reasserted immediately. The NS9750 FIFO Interrupt Status registers pertain to DMA mode only; Note: direct, or processor-controlled, mode is not supported at this time. The following control signals are considered “don’t care”...
Page 794 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s Device endpoint status Table 449 defines the device endpoint status provided for each endpoint FIFO.
Page 795: Fifo Interrupt Status 0 Register
FIFO Interrupt Status 0 register Address: 9010 3000 NACK ERROR ACK2 Reserved Register bit assignment Bits Access Mnemonic D31:16 Not used RW1TC ACK2 RW1TC NACK2 RW1TC ERROR2 D12:08 Reserved RW1TC ACK1 RW1TC NACK1 RW1TC ERROR1 D04:00 Reserved Table 450: FIFO Interrupt Status 0 register FIFO Interrupt Status 1 register Address: 9010 3010 Reserved...
Page 796 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s NACK ERROR ACK6...
Page 797: Fifo Interrupt Status 2 Register
Bits Access Mnemonic RW1TC NACK3 RW1TC ERROR3 D04:00 Reserved Table 451: FIFO Interrupt Status 1 register FIFO Interrupt Status 2 register Address: 9010 3020 NACK ERROR Reserved NACK ERROR ACK8 Reserved Register bit assignment Bits Access Mnemonic RW1TC ACK10 RW1TC NACK10 RW1TC ERROR10...
Page 798 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s Bits Access D20:16...
Page 799: Fifo Interrupt Status 3 Register
FIFO Interrupt Status 3 register Address: 9010 3030 NACK ERROR Reserved Register bit assignment Bits Access Mnemonic D31:16 Reserved RW1TC ACK12 RW1TC NACK12 RW1TC ERROR12 D12:08 Reserved RW1TC ACK11 RW1TC NACK11 RW1TC ERROR11 D04:00 Reserved Table 453: FIFO Interrupt Status 3 register Reserved NACK ERROR...
Page 800: Fifo Interrupt Enable Registers
U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s FIFO Interrupt Enable registers The FIFO Interrupt Enable registers contain the interrupt enable information for the device block FIFOs.
Page 801: Fifo Interrupt Enable 1 Register
FIFO Interrupt Enable 1 register Address: 9010 3014 NACK ERROR ACK6 Reserved NACK ERROR ACK4 Reserved Register bit assignment Bits Access Mnemonic ACK6 NACK6 ERROR6 D28:24 Reserved ACK5 NACK5 ERROR5 D20:16 Reserved ACK4 NACK4 ERROR4 D12:08 Reserved Table 455: FIFO Interrupt Enable 1 register NACK ERROR ACK5...
Page 802 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s Bits Access D04:00...
Page 803 Bits Access Mnemonic ERROR9 D20:16 Reserved ACK8 NACK8 ERROR8 D12:08 Reserved ACK7 NACK7 ERROR7 D04:00 Reserved Table 456: FIFO Interrupt Enable 2 register FIFO Interrupt Enable 3 register Address: 9010 3034 Not used NACK ERROR Reserved Reset Description Generate an interrupt when ERROR9 in FIFO Interrupt Status 2 register is asserted.
Page 804: Fifo Packet Control Registers
U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s Register bit assignment Bits Access...
Page 805: Fifo Status And Control Registers
used Register bit assignment Bits Access D31:30 D29:20 D19:16 D15:00 Table 458: FIFO Packet Control registers FIFO Status and Control registers Address: 9010 3100 / 3108 / 3110 / 3118 / 3120 / 3128 / 3130 / 3138 / 3140 / 3148 / 3150 / 3158 / 3160 The FIFO Status and Control registers contain additional status and control information for the device block FIFOs.
Page 806 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s STATE Register bit assignment Bits...
Page 807 Bits Access Mnemonic D15:14 STATE D11:00 Table 459: FIFO Status and Control registers U S B C o n t r o l l e r M o d u l e Reset Description State field Defines the state of the endpoint after the most recent communication with the USB device module.
Page 808 U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s 7 8 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 809 U S B C o n t r o l l e r M o d u l e 7 8 5 w w w . d i g i e m b e d d e d . c o m...
Page 811 Timing his chapter provides the electrical specifications, or timing, integral to the operation of the NS9750. Timing includes information about DC and AC characteristics, output rise and fall timing, and crystal oscillator specifications. 7 8 7...
Page 812: Electrical Characteristics
E l e c t r i c a l c h a r a c t e r i s t i c s Electrical characteristics The NS9750 operates at a 1.5V core, with 3.3V I/O ring voltages. Absolute maximum ratings Permanent device damage can occur if the absolute maximum ratings are exceeded for even an instant.
Page 813: Maximum Power Dissipation
Total @ 1.05 W 125 MHz Core 0.65 W 0.4 W Table 462: NS9750 power dissipation Typical power dissipation The next table shows typical power dissipation for I/O and core. CPU clock Total@ 200 MHZ Operation Sleep mode with wake up on...
Page 814: Dc Electrical Characteristics
D C e l e c t r i c a l c h a r a c t e r i s t i c s DC electrical characteristics DC characteristics specify the worst-case DC electrical performance of the I/O buffers that are guaranteed over the specified temperature range.
Page 815: Outputs
Symbol Parameter Input low level Differential input sensitivity Differential common mode range Table 464: USB DC electrical inputs Notes: |(usb_dp) – (usb_dm)| Includes V range. Outputs All electrical outputs are 3.3V interface. Parameter High-level output voltage (LVTTL) Low-level output voltage (LVTTL) PCI high-level output voltage PCI low-level output voltage Table 465: DC electrical outputs...
Page 816: Reset And Edge Sensitive Input Timing Requirements
A maximum rise and fall time must be met to ensure that reset and edge sensitive inputs are handled correctly. With Digi processors, the maximum is 500 nanoseconds as shown: reset_n or positive edge input...
Page 817 If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise and fall time requirement, the signal must be buffered with a Schmitt trigger device. Here are sample Schmitt trigger device part...
Page 818: Power Sequencing
P o w e r s e q u e n c i n g Power sequencing Use these requirements for power sequencing: 7 9 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 819: Memory Timing
Memory timing All AC characteristics are measured with 35pF, unless otherwise noted. Note: Memory timing contains parameters and diagrams for both SDRAM and SRAM timing. Table 467 describes the values shown in the SDRAM timing diagrams (Figure 104 through Figure 112). Parm Description data input setup time to rising...
Page 820: Sdram Burst Read (16-Bit)
M e m o r y t i m i n g SDRAM burst read (16-bit) clk_out<3:0> data<31:16> addr Note-1 data_mask<3:0> dy_cs_n<3:0>* ras_n cas_n we_n Figure 104: SDRAM burst read (16-bit) timing Notes: This is the bank and RAS address. This is the CAS address.
Page 821: Sdram Burst Read (16-Bit), Cas Latency = 3
SDRAM burst read (16-bit), CAS latency = 3 clk_out<3:0> data<31:16> addr Note-1 data_mask<3:0> dy_cs_n<3:0>* ras_n cas_n we_n Figure 105: SDRAM burst read (16-bit), CAS latency = 3 timing Notes: This is the bank and RAS address. This is the CAS address. read Note-2 w w w .
Page 822: Sdram Burst Write (16-Bit)
M e m o r y t i m i n g SDRAM burst write (16-bit) clk_out<3:0> data<31:0> addr data_mask<3:2> data_mask<1:0>* dy_cs_n<3:0>* ras_n cas_n we_n Figure 106: SDRAM burst write (16-bit) timing Notes: This is the bank and RAS address. This is the CAS address.
Page 823: Sdram Burst Read (32-Bit)
SDRAM burst read (32-bit) prechg clk_out<3:0> data<31:0> addr data_mask<3:0>* dy_cs_n<3:0>* ras_n cas_n we_n Figure 107: SDRAM burst read (32-bit) timing Notes: This is the bank and RAS address. This is the CAS address. active read cas lat Note-1 Note-2 w w w . d i g i e m b e d d e d . c o m T i m i n g data-A data-B...
Page 824: Sdram Burst Read (32-Bit), Cas Latency = 3
M e m o r y t i m i n g SDRAM burst read (32-bit), CAS latency = 3 clk_out<3:0> data<31:0> addr data_mask<3:0>* dy_cs_n<3:0>* ras_n cas_n we_n Figure 108: SDRAM burst read (32-bit), CAS latency = 3 timing Notes: This is the bank and RAS address.
Page 825: Sdram Burst Write (32-Bit)
SDRAM burst write (32-bit) prechg clk_out data<31:0> addr data_mask<3:0>* dy_cs_n<3:0> ras_n cas_n we_n Figure 109: SDRAM burst write (32-bit) timing Notes: This is the bank and RAS address. This is the CAS address. active wr d-A Note-1 Note-2 w w w . d i g i e m b e d d e d . c o m data-B data-C data-D...
Page 826: Sdram Load Mode
M e m o r y t i m i n g SDRAM load mode clk_out<3:0> dy_cs_n<3:0>* ras_n cas_n we_n addr<11:0> Figure 110: SDRAM load mode timing 8 0 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e op code...
Page 827: Sdram Refresh Mode
SDRAM refresh mode prechg clk_out<3:0> dy_cs0_n dy_cs1_n dy_cs2_n dy_cs3_n ras_n cas_n we_n Figure 111: SDRAM refresh mode timing Clock enable timing clk_out<3:0> clk_en<3:0> SDRAM cycle Figure 112: Clock enable timing CS0 rf CS1 rf CS2 rf CS3 rf clk_enable.td w w w . d i g i e m b e d d e d . c o m T i m i n g 8 0 3...
Page 828 M e m o r y t i m i n g Table 468 describes the values shown in the SRAM timing diagrams (Figure 113 through Figure 118). Parm Description clock high to data out valid data out hold time from clock high clock high to address valid address hold time from clock high clock high to st_cs_n low...
Page 829: Static Ram Read Cycles With 0 Wait States
Static RAM read cycles with 0 wait states CPU clock / 2 data<31:0> addr<27:0> st_cs_n<3:0> oe_n byte_lane<3:0> Figure 113: Static RAM read cycles with 0 wait states timing WTRD = 1 WOEN = 1 If the PB field is set to 1, all four 16-bit, and 8-bit read cycles.
Page 830: Static Ram Asynchronous Page Mode Read, Wtpg = 1
M e m o r y t i m i n g Static RAM asynchronous page mode read, WTPG = 1 Note-1 CPU clock / 2 data<31:0> addr<27:0> Note-3 st_cs_n<3:0> oe_n Note-7 byte_lane<3:0> Figure 114: Static RAM asynchronous page mode read, WTPG = 1 timing WTPG = 1 WTRD = 2 If the PB field is set to 1, all four...
Page 831: Static Ram Read Cycle With Configurable Wait States
Static RAM read cycle with configurable wait states CPU clock / 2 data<31:0> addr<27:0> Note-1 st_cs_n<3:0> oe_n Note-1 byte_lane<3:0> Note-1 Figure 115: Static RAM read cycle with configurable wait states WTRD = from 1 to 15 WOEN = from 0 to 15 If the PB field is set to 1, all four 16-bit, and 8-bit read cycles.
Page 832: Static Ram Sequential Write Cycles
M e m o r y t i m i n g Static RAM sequential write cycles CPU clock / 2 data<31:0> addr<27:0> st_cs_n<3:0> we_n byte_lane<3:0> byte_lane[3:0] as WE* Note1 Figure 116: Static RAM sequential write cycles WTWR = 0 WWEN = 0 During a 32-bit transfer, all four During a 16-bit transfer, two...
Page 833: Static Ram Write Cycle
Static RAM write cycle CPU clock / 2 data<31:0> addr<27:0> st_cs_n<3:0> we_n byte_lane<3:0> byte_lane[3:0] as WE* Note-1 Figure 117: Static RAM write cycle WTWR = 0 WWEN = 0 During a 32-bit transfer, all four During a 16-bit transfer, two During an 8-bit transfer, only one Note: If the PB field is set to 0, the...
Page 834: Static Write Cycle With Configurable Wait States
M e m o r y t i m i n g Static write cycle with configurable wait states CPU clock / 2 data<31:0> addr<17:0> st_cs_n<3:0> we_n byte_lane<3:0> byte_lane[3:0] as WE* Note-4 Figure 118: Static write cycle with configurable wait states WTWR = from 0 to 15 WWEN = from 0 to 15 The WTWR field determines the length on the write cycle.
Page 835: Slow Peripheral Acknowledge Timing
Slow peripheral acknowledge timing This table describes the values shown in the slow peripheral acknowledge timing diagrams. Parameter Description clock high to data out valid data out hold time from clock high clock high to address valid address hold time from clock high clock high to st_cs_n low clock high to st_cs_n high clock high to we_n low...
Page 836: Slow Peripheral Acknowledge Read
M e m o r y t i m i n g Slow peripheral acknowledge read clk_out<3:0> data<31:0> addr<27:0> st_cs_n<3:0> oe_n byte_lane<3:0> ta_strb Slow peripheral acknowledge write clk_out<3:0> data<31:0> addr<27:0> st_cs_n<3:0> we_n byte_lane<3:0> ta_strb 8 1 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e 50ns 100ns 50ns...
Page 837: Ethernet Timing
Ethernet timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 470 describes the values shown in the Ethernet timing diagrams (Figure 119 and Figure 120). Parameter Description MII tx_clk to txd, tx_en, tx_er MII rxd, rx_en, rx_er setup to rx_clk rising MII rxd, rx_en, rx_er hold from rx_clk rising mdio (input) setup to mdc rising mdio (input) hold from mdc rising...
Page 838: Ethernet Mii Timing
E t h e r n e t t i m i n g Ethernet MII timing tx_clk txd[3:0],tx_en,tx_er rx_clk rxd[3:0],rx_en,rx_er cam_req cam_reject mdio (input) mdio (output) Figure 119: Ethernet MII timing 8 1 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 839: Ethernet Rmii Timing
Ethernet RMII timing ref_clk txd[1:0],tx_en rxd[1:0],crs,rx_er mdio (input) mdio (output) Figure 120: Ethernet RMII timing w w w . d i g i e m b e d d e d . c o m T i m i n g 8 1 5...
Page 840: Pci Timing
P C I t i m i n g PCI timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 471 and Table 472 describe the values shown in the PCI timing diagrams (Figure 121 through Figure 127). Parameter Description pci_clk_in to signal valid delay...
Page 841 Parameter Description pci_clk_in to signal valid delay Input setup to pci_clk_in Input hold from pci_clk_in pci_clk_in to signal active pci_clk_in to signal float pci_clk_out high time pci_clk_out low time pci_clk_in cycle time pci_clk_in high time pci_clk_in low time Table 472: CardBus timing characteristics Notes: Minimum times are specified with 0pf and maximum times are specified with 30pf.
Page 842: Internal Pci Arbiter Timing
Figure 122: PCI burst write from NS9750 timing The functional timing for Note: response from the target. 8 1 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 843: Pci Burst Read From Ns9750 Timing
PCI burst read from NS9750 timing pci_clk_in frame_n addr ad[31:0] cbe_n[3:0] irdy_n trdy_n devsel_n Figure 123: PCI burst read from NS9750 timing The functional timing for Note: the fastest possible response from the target. PCI burst write to NS9750 timing pci_clk_in frame_n ad[31:0] addr...
Page 844: Pci Burst Read To Ns9750 Timing
3x pci_clk_in devsel_n Figure 125: PCI burst read to NS9750 timing The functional timing for valid read data on Note: actual response time will depend on when the PCI bridge gets access to the AHB bus internal to NS9750.
Page 845 C timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 473 describes the values shown in the I Parm Description iic_sda to iic_scl START hold time iic_scl low period iic_scl high period iic_scl to iic_sda DATA hold time iic_sda to iic_scl DATA setup time iic_scl to iic_sda START setup time iic_scl to iic_sda STOP setup time...
Page 846: Lcd Timing
L C D t i m i n g LCD timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 474 describes the values shown in the LCD timing diagrams (Figure 129 through Figure 135). Parm Description Horizontal front porch blanking Horizontal sync width Horizontal period...
Page 847 Parm Description CLCP to data/control (see notes 7 and 8) CLCP high (see notes 8, 9) CLCP low (see notes 8, 9) TFT VSYNC active to HSYNC active (see note 8) TFT VSYNC active to HSYNC inactive STN VSYNC active to HSYNC inactive STN HSYNC inactive to VSYNC inactive...
Page 848: Horizontal Timing For Stn Displays
L C D t i m i n g These data widths are supported: — 4-bit mono STN single panel — 8-bit mono STN single panel — 8-bit color STN single panel — 4-bit mono STN dual panel (8 bits to LCD panel) —...
Page 849: Vertical Timing For Stn Displays
Vertical timing for STN displays CLFP CLLP CLD[7:0] Blank Lines Figure 130: Vertical timing parameters for STN displays Horizontal timing for TFT displays CLLP CLCP CLAC CLD[23:0] Figure 131: Horizontal timing parameters for TFT displays Vertical timing for TFT displays CLFP CLLP CLAC...
Page 850: Hsync Vs Vsync Timing For Stn Displays
L C D t i m i n g HSYNC vs VSYNC timing for STN displays CLFP CLLP Figure 133: HSYNC vs VSYNC timing for STN displays HSYNC vs VSYNC timing for TFT displays CLFP CLLP Figure 134: HSYNC vs VSYNC timing for TFT displays LCD output timing CLD[23:0],CLLP,CLFP,CLLE,CLAC Figure 135: LCD output timing...
Page 851: Spi Timing
SPI timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 475 describes the values shown in the SPI timing diagrams (Figure 136 through Figure 139). Parm Description SPI master parameters SPI enable low setup to first SPI CLK out rising SPI enable low setup to first SPI CLK out falling...
Page 852 S P I t i m i n g Parm Description SP14 SPI enable low setup to first SPI CLK in rising SP15 SPI enable low setup to first SPI CLK in falling SP16 SPI data in setup to SPI CLK in rising SP17 SPI data in hold from SPI CLK in...
Page 853: Spi Master Mode 0 And 1: 2-Byte Transfer
= 10pf for all outputs. load SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel B/A/C/D Control Register A. SPI master mode 0 and 1: 2-byte transfer (see note 7) SPI CLK Out (Mode 0) SPI CLK Out (Mode 1) SPI Enable SPI Data Out...
Page 854: Spi Slave Mode 0 And 1: 2-Byte Transfer
S P I t i m i n g SPI slave mode 0 and 1: 2-byte transfer (see note 7) SP14 SPI CLK In (Mode 0) SP15 SPI CLK In (Mode 1) SPI Enable SPI Data Out SPI Data In Figure 138: SPI slave mode 0 and 1 (2-byte transfer) SPI slave mode 2 and 3: 2-byte transfer (see note 7)
Page 855: Ieee 1284 Timing
IEEE 1284 timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 476 describes the values shown in the IEEE 1284 timing diagram (Figure 140). Parm Description Busy-while-Strobe Busy high to nAck low Busy high nAck low nAck high to Busy low Table 476: IEEE 1284 timing parameters Notes:...
Page 856: Usb Timing
U S B t i m i n g USB timing Table 477 and Table 478 describe the values shown in the USB timing diagrams (Figure 141 through Figure 143). Parm Description Rise time (10% – 90%) Fall time (10% – 90%) Differential rise and fall time matching Driver output resistance Table 477: USB full speed timing parameters...
Page 857: Usb Differential Data Timing
USB differential data timing usb_dp usb_dm Figure 141: USB differential data USB full speed load timing usb_dp usb_dm Figure 142: USB full speed load Full Speed Buffer w w w . d i g i e m b e d d e d . c o m Rs - external resistor = 50pf = 50pf...
Page 858: Usb Low Speed Load
U S B t i m i n g USB low speed load usb_dp usb_dm Figure 143: USB low speed load 8 3 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Low Speed Buffer Rs - external resistor = 200pf to 600pf...
Page 859: Reset And Hardware Strapping Timing
Reset and hardware strapping timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 479 describes the values shown in the reset and hardware strapping timing diagram (Figure 144). Parm Description reset_n minimum time reset_n to reset_done Table 479: Reset and hardware strapping timing parameters Note: The hardware strapping pins are latch 5 clock cycles after...
Page 860: Jtag Timing
J T A G t i m i n g JTAG timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 480 describes the values shown in the JTAG timing diagram (Figure 145). Parm Description tms (input) setup to tck rising tms (input) hold to tck rising tdi (input) setup to tck rising tdi (input) hold to tck rising...
Page 861: Clock Timing
Clock timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: The next three timing diagrams pertain to clock timing. USB crystal/external oscillator timing Table 481 describes the values shown in the USB crystal/external oscillator timing diagram (Figure 146). Parm Description x1_usb_osc cycle time...
Page 862: Lcd Input Clock Timing
C l o c k t i m i n g LCD input clock timing Table 482 describes the values shown in the LCD input clock timing diagram (Figure 147). Parm Description lcdclk cycle time lcdclk high time lcdclk low time Table 482: LCD input clock timing parameters Note: The clock rate supplied on...
Page 863: System Pll Bypass Mode Timing
System PLL bypass mode timing Table 483 describes the values shown in the system PLL bypass mode timing diagram (Figure 148). Parm Description x1_sys_osc cycle time x1_sys_osc high time x1_sys_osc low time Table 483: System PLL bypass mode timing parameters Note: The system PLL can be bypassed.
Page 865 Packaging he NS9750 is a complete system-on-chip processor, and includes Ethernet, display support, and a robust peripheral set. NS9750 dimensions and pinout are shown on the following pages. 8 4 1...
Page 866 Figure 149 displays the top view and dimensions of the NS9750. Figure 150 displays the side and bottom views and dimensions. 35.0 35.0 Figure 149: NS9750 top view 8 4 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e...
Page 867 0.6 + 0.1 1.27 0.35 0.20 Figure 150: NS9750 side and bottom views 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0.75 + 0.15 0.15...
Page 868 Figure 151 shows the layout of the NS9750, for use in setting up the board. GPIO45 GPIO49 PHY_INTn TXEN TXD_2 RXER (VDDS) GPIO44 GPIO48 MDIO TXD_0 TXD_3 GPIO43 (GND) USB_DP GPIO46 TXER TXD_1 GPIO39 GPIO42 (VDDC) USB_DM GPIO47 VDDS VDDS...
Page 869: Product Specifications
Product specifications These tables provide additional information about the NS9750. ROHS substance Lead Mercury Cadmium Hexavalent Chromium Polybrominated biphenyls Polybrominated diphenyl ethers Table 484: NS9750 ROHS specifications Component Weight [mg] Chip 27.037 Frame 1841.616 Bonding wire 6.990 Ag paste 3.400 Epoxy resin 1920.177...
Page 870 Solder ball 592.400 Total weight 4391.620 Table 485: NS9750 materials sheet 8 4 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e Material CAS no.
Page 871 Index Numerics 10/100 Ethernet MAC 1284 parallel peripheral port 16-bit byte gap counter 689 , 690 16-bit maximum buffer counter 16-bit Thumb instruction set 48 , 50 32-bit ARM instruction set 48 , 50 8-bit Java instruction set absolute maximum ratings access sequencing and memory width, dynamic memory controller access sequencing and memory width,...
Page 872 about cache format Jazelle (Java) Memory Management Unit. See system register addresses ARM926EJ-S RISC processor attributes, system control module Back-to-Back Inter-Packet_Gap register bandwidth requirements BBus master and slave modules BBus bridge arbitration (masters and slaves) arbitration and multiplexing bandwidth requirements BBus Bridge Interrupt Enable BBus Bridge Interrupt Status Buffer Descriptor Pointer register...
Page 873 BBus peripheral address map BBus slave and DMA interface module 677 - 705 CPU mode DMA mode register map BBus subsystem BBus utility 521 - 542 ARM Wake-up register BBus DMA Interrupt Enable register BBus DMA Interrupt Status register BBus Monitor register Endian Configuration register GPIO Configuration register options...
Page 874 Configuration Address Data Port register Configuration Address Port register Configuration register Configuration register, memory configuring the NS9750 for CardBus support context (static) RAM control in packets control logic, BBus bridge Control register, memory conventions, documentation...
Page 875 R3, Domain Access Control register 61 , 98 R4 register R5, Fault Status registers R6, Fault Address register 64 , 97 R7, Cache Operations register R8, TLB Operations register R9, Cache Lockdown register system control processor registers 51 - 77 addresses summary terms and abbreviations...
Page 876 DMA read. See also peripheral transfers. DMA Status and Interrupt Enable register DMA Status/Interrupt Enable register DMA system DMA transfer executing two-channel transfer external-peripheral-initiated processor-initated DMA transfer status DMA write. See also memory transfers. documentation conventions domain faults downstream port (USB) downstream transactions dummy default master dynamc memory controller...
Page 877 register Collision Window/Retry register control and status registers definition diagram Ethernet front-end (EFE) module. See also Ethernet front-end 323-333 module. Ethernet front-end features Ethernet front-end module Ethernet General Control Register Ethernet General Control Register Ethernet General Status register Ethernet Interrupt Enable register Ethernet Interrupt Status register Ethernet MAC 317 - 322...
Page 878 TX Error Buffer Descriptor Pointer Ethernet front-end module about Ethernet slave interface features interrupts power down mode receive packet processor resets transferring a frame to system transmit packet processor transmitting a frame to the Ethernet Ethernet General Control Register #1 Ethernet General Control Register #2 Ethernet General Status register Ethernet interface pinout...
Page 879 fly-by mode fly-by peripheral to memory operations Forward Address register Forward Command DMA Control register Forward Command FIFO Read register Forward Data DMA Control register Forward Data FIFO Read register FULL bit 476 , 506 FULL bit, Ethernet 326 , 328 gated timer GEN ID register general purpose I/O.
Page 880: I2C Timing
I bit, Ethernet bus arbitration command interface Command Transmit Data register Configuration register external addresses locked interrupt driven mode Master Address register master module commands master module flowchart master software driver master/slave interface module physical bus register addresses Slave Address register slave module commands slave module flowchart Status Receive Data register...
Page 881 timing diagram IEEE 1284 General Configuration register IEEE 1284 timing individual interrupts, LCD industry-standard Ethernet interfaces RMII initializing PLL parameters initiating a DMA transfer, two channel (AHB) Int Config registers (0-31) register address mapping interrupt aggregation INTERRUPT bit interrupt bit interrupt codes Interrupt Configuration register interrupt controller...
Page 882 color STN panels features functional overview interrupts master bus error interrupt next base update interrupt vertical compare interrupt LCD panel resolution LCD timing diagrams LCDControl register LCDInterrupt register LCDINTRENABLE register LCDLPBASE register LCDLPCURR register LCDPalette register LCDStatus register LCDTiming0 register LCDTiming1 register LCDTiming2 register LCDTiming3 register...
Page 883 maximum power dissipation Media Independent Interface. See memory controller 115 - 240 access sequencing and memory width, dynamic memory controller access sequencing and memory width, static memory controller address connectivity address mapping, dynamic memory controller 163 - 201 bootstrap signals bootstrap signals, memory controller bus turnaround...
Page 884: Write Protection
(LNBU) nibble mode data transfer cycle Non Back-to-Back Inter-Packet-Gap register noncacheable instruction fetches AHB behavior NS9750 10/100 Ethernet MAC 1284 parallel peripheral port clock generation/system pins pinout clock generator configuring for CardBus support definition 1 , 2...
Page 885 Ethernet interface pinout external interrupts external peripheral external system bus interface features 2 - 7 general purpose I/O (GPIO) general purpose timers and counters GPIO MUX I2C pinout I2C port JTAG interface pinout LCD controller LCD module signals operating grades and ambient temperatures PCI CardBus port PCI pinout...
Page 886 461 - 465 central resource functions Configuration Address Data Port register Configuration Address Port register configuration and status registers configuration registers configuring the NS9750 for CardBus support definition device selection for configuration Endian configuration features functionality 405 - 407 interrupts...
Page 887 PCI Arbiter Configuration register PCI Arbiter Interrupt Enable register PCI Arbiter Interrupt Status register PCI Base Address registers PCI BIST register PCI Bridge Address Translation Control register PCI Bridge AHB Error Address register PCI Bridge AHB to PCI Memory Address Translate 0 register PCI Bridge AHB to PCI Memory Address Translate 1 register...
Page 888 Ethernet interface GPIO MUX JTAG interface NS9750 PCI interface reserved pins system memory interface USB interface pixel serializer PLL configuration PLL Configuration register PLL multiplier values pll_test_n truth/termination table Port Control register Port Status register, host Port Status register, peripheral...
Page 889 recommended operating conditions Reduced Media Independent Interface. RMII register hash tables regular timer relinquishing the bus reserved pins reset and edge sensitive input timing requirements Reset and hardware strapping timing Reset and Sleep Control register reset function boot sequence master reset RESET DONE as input RESET DONE as output reset values...
Page 890 Serial Channel B/A/C/D Control Serial Channel B/A/C/D FIFO Data Serial Channel Status Register A serial port control and status serial port performance SPI timing diagrams structure transmit FIFO interface serial controller, UART bit-rate examples bit-rate generator features FIFO management receive FIFO interface transmit FIFO interface framing structure functions...
Page 891: Extended Wait Transfers
SPI mode individual mode definition individual modes See also serial controller, SPI. SPI timing 827 - 830 SPI-EEPROM boot logic 484 - 489 ARM (memory) boot configuration example memory controller configuration spike filter SPLIT transfers state machine static (context) RAM Static Memory Configuration 0-3 registers static memory controller...
Page 892: Features
system control module Active Interrupt Level Status AHB Arbiter Gen Configuration bootstrap initialization BRC channel assignment BRC0, BRC1, BRC2, BRC3 registers bus arbiter configuration bus interconnection Clock Configuration register definition External Interrupt 0-3 Control features Gen ID register general purpose timers/counters Int Config registers (0-31) register address mapping interrupt controller...
Page 893 R0, ID code and cache type status registers 55 - 57 R1, Control register 58 - 60 R10, TLB Lockdown register R11 register R12 register R13, Process ID register 75 - 77 R14 register R15, Test and debug register R2, Translation Table Base register R3, Domain Access Control register 61 , 98...
Page 894 timing controller, LCD TLB structure transaction ordering, AHB-to-PCI bridge transferring a frame to system memory, Ethernet translation faults Translation Lookaside Buffer (TLB) transmission error handling, USB transmit broadcast packet counter transmit buffer descriptor format Ethernet Transmit Buffer Descriptor Pointer Offset register transmit byte counter transmit deferral packet counter...
Page 895: Static Memory Controller
FIFO Interrupt Status 0 register FIFO Interrupt Status 1 register FIFO Interrupt Status 2 register FIFO Interrupt Status 3 register FIFO Interrupt Status registers FIFO Packet Control registers FIFO Status and Control registers Global Interrupt Enable register Global Interrupt Status register HcBulkCurrentED register HcBulkHeadED register HcCommandStatus register...
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Digi NS9750 Hardware Reference Manual

Table of Contents

Chapter 1 : about NS9750

Chapter 2 : NS9750 Pinout

Chapter 3 : Working with the CPU

Chapter 5 : M E M O R y C O N T R O L L E R

Chapter 4 : System Control Module

Chapter 7 : PCI-To-AHB Bridge

Chapter 8 : Bbus Bridge

Chapter 9 : Bbus DMA Controller

Chapter 10 : Bbus Utility

Chapter 16 : USB Controller Module

Chapter 11 : I2C Master/Slave Interface

Chapter 12 : LCD Controller

Chapter 13 : Serial Control Module: UART

Chapter 14 : Serial Control Module: SPI

Chapter 15 : IEEE 1284 Peripheral Controller

Chapter 17 : Timing

Chapter 18 : Packaging

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Summary of Contents for Digi NS9750