Mii Management Read Data Register; Mii Management Indicators Register - Digi NS9750 Hardware Reference Manual

Single chip 0.13μm cmos network-attached processor
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MII Management Read Data register

Address: A060 0430
31
15
Register bit assignment
Bits
D31:16
D15:00
Table 222: MII Management Read Data register

MII Management Indicators register

Address: A060 0434
31
15
30
29
28
27
14
13
12
11
Access
Mnemonic
N/A
Reserved
R
MRDD
30
29
28
27
14
13
12
11
E t h e r n e t C o m m u n i c a t i o n M o d u l e
26
25
24
23
Reserved
10
9
8
7
MRDD
Reset
Description
N/A
N/A
0x0000
MII read data
Read data is obtained by reading from this register
after an MII Management read cycle. An MII
Management read cycle is executed by loading the
MII Management Address register, then setting the
READ bit to 1 in the MII Management Command
register (see page 360). Read data is available after the
BUSY bit in the MII Management Indicators register
(see page 363) returns to 0.
26
25
24
23
Reserved
10
9
8
7
Reserved
w w w . d i g i e m b e d d e d . c o m
22
21
20
19
6
5
4
3
22
21
20
19
6
5
4
3
MIILF
VALID
18
17
16
2
1
0
18
17
16
2
1
0
N
SCAN
BUSY
3 6 3

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