Ethernet Interface - Digi NS9750 Hardware Reference Manual

NS9750
Figure 7: NS9750 clock enable configuration

Ethernet interface

Pin #
AB1
AA2
AC1
AA3
AB2
T3
V2
W1
V1
Table 5: Ethernet interface pinout
clk_en[n]
reset_done
3.3V
Signal name
MII RMII
col N/C
crs crs_dv
enet_phy_i enet_phy_i
nt_n nt_n
mdc mdc
mdio mdio
rx_clk ref_clk
rx_dv N/C
rx_er rx_er
rxd[0] rxd[0]
U1
0 = B0 TO A
6 1
S B1
5 4
V+ A
2 3
GND B0
2.4K
NC7SB3157
ohm
OD Description
U/D (mA) I/O
MII
I Collision
I Carrier sense
U I Ethernet PHY
interrupt
4 O MII management
interface clock
U 2 I/O MII management data
I Receive clock
I Receive data valid
I Receive error
I Receive data bit 0
w w w . d i g i e m b e d d e d . c o m
N S 9 7 5 0 P i n o u t
CKE
3.3V
SDRAM
RMII
Pull low external to
NS9750
Carrier sense
Ethernet PHY
interrupt
MII management
interface clock
MII management data
Reference clock
Pull low external to
NS9750
Optional signal; pull
low to NS9750 if not
used
Receive data bit 0
2 5