Status Register; Configuration Register - Digi NS9750 Hardware Reference Manual

Status register

Address: A070 0004
The Status register provides memory controller status information.
31
15
Register bit assignment
Bits
D31:03
D02
D01
D00
Table 139: Status register

Configuration register

Address: A070 0008
30 29 28 27
14 13 12 11
Access Mnemonic
N/A Reserved
R SA
R WBS
R BUSY
26 25 24 23
Reserved
10 9 8 7
Reserved
Description
N/A (do not modify)
Self-refresh acknowledge (SREFACK)
0 Normal mode
1 Self refresh mode (reset value on
Indicates the memory controller operating mode.
Write buffer status
0 Write buffers empty (reset value on
1 Write buffers contain data
Enables the memory controller to enter low-power mode or disabled
mode clearly.
Busy
0 Memory controller is idle (reset value on
1 Memory controller is busy performing memory transactions,
commands, or auto-refresh cycles, or is in self-refresh mode
(reset value on
reset_n
Ensures that the memory controller enters the low-power or disabled
state cleanly by determining whether the memory controller is busy.
w w w . d i g i e m b e d d e d . c o m
M e m o r y C o n t r o l l e r
22 21 20 19
6 5 4 3
)
reset_n
)
reset_n
HRESETn
and )
HRESETn
18 17 16
2 1 0
SA WBS BUSY
)
2 0 7