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01
Processor register test about to start.and NMI to be Init.
02 NMI is disable, power on delay starting.
03 Power on delay complete. To check soft reset/power on.
05 Soft reset/power on determined. Going to disable Cache.
06 Post code to be uncompressed.
08 Post code is uncompressed. CMOS checksum calculation to
be done next.
09 CMOS checksum calculation is done, CMOS Diag byte
written. CMOS init. to begin.
0A CMOS Init. done. CMOS status register about to Init. for
Date and Time.
0B CMOS status register Init done. Any Init. before KB BAT
to be done next.
0C KB I/B free. Going to issue the BAT command to KB.
0D BAT command to KB is issued. Going to verify the BAT
command.
0E KB BAT result verified. Any Init. after KB BAT to be done.
0F Init. after KB BAT done. KB byte to be written next.
10 KB command byte is written. Going to issue P-23,24
blocking/unblocking command.
11 P-23,24 of KB is block/unblock. Going to check pressing
<INS> key during power-on.
12 Checking for pressing <INS> key during power on done.
Going to disable DMA and Interrupt controller.
13 DMA controller #1, #2, Interrupt controller #1,#2 disable.
Vide display is disable and port-B is Init. Chipset Init about
begin.
14 Chipset Init ower. 8254 timer test about to start.
19 8254 timer test over. About to start memory refresh test.
1A Momory Refresh line is togging. Going to check 16 micro
second ON/OFF time.
20 Memory Refresh period 30 micro second test complete.
Base 64K test to start.
S1462-001-01
60
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