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Appendix A: Post Codes
EISA POST codes are typically output to port address 300h. ISA
POST codes are typically output to port address 80h ( Award BIOS)
POST
N a m e
C 0
Turen
off
Chipset
C a c h e
1
Processor
Test
2
Processor
Test
3
Initialize
Chips
4
Test
Memory
Refresh
Toggle
5
Blank
video,
I n i t i a l i z e
K e y b o a r d
6
R e s e r v e d
7
Test
CMOS
Interface
and
Battery
Status
B E
Chipset
Default
C1
M e m o r y
presense
test
C 5
Early
shadow
C 6
Cache
presence
t e s t
8
setup
low
m e m o r y
9
Early
cache
I n i t i a l i z e
A
Setup
Interrupt
Vector
Table
B
Test
CMOS
C h e c k s u m
S1462-001-01
OEM
specific-Cache
Processor
Status
1
Test
the
following
zero,
sign,
overflow.
these
flags,
verify
they
flag
off
and
verify
it
2
Read/Write/Verify
all
SP,
and
BP
with
Disable
NMI,
PIE,
video,
parity
checking,
co-processor.
Clear
timer
0,1
and
2,
including
known
state.
Initialize
Initialize
interrupt
controllers
EISA
extended
RAM
must
be
periodically
keep
the
memory
assures
that
the
working
properly.
Keyboard
initialization.
Verifies
CMOS
is
bad
battery.
Programs
chipset
registers
d e f a u l t s
OEM
specific-Test
to
OEM
Specific-Early
external
cache
size
early
chipset
initialization.
test.
OEM
chip
set
memory.
Test
first
Cyrix
CPU
Initialization.
Initialization
first
120
SPURIOUS_INT-HDLR
Fh
according
to
RAM
Test
CMOS
RAm
key
is
pressed,
56
control
(1
FLAGS)
Verification.
processoe
statue
flags
The
BIOS
will
set
each
are
set,
then
turn
each
is
off
CPU
registers
except
data
pattern
FFand
00
AIE,
UEI,
SQWV.
Disable
DMA.
Reset
math
all
page
registers.
set
EISA
timer
to
DMA
controllers
0
and
0
and
1.
Initialize
regesters.
refreshed
in
order
form
decaying.
This
functon
memory
refresh
functoin
working
properly,
detects
with
power
on
size
on
board
memory.
shadow
enable
for
fast
detection
Memory
presence
routines.
Clear
low
64K
64K
memory.
Cache
initialization
interrupt
vectors
with
and
initialize
INT
INT_TBL.
Checksum,
if
bad,
or
insert
load
defaults.
carry,
of
SS,
Initizlize
a
1.
to
is
a
BIOS
boot
00h-1
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