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Analog Devices AD9380 Manual
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Analog Devices AD9380 Manual

Analog Devices AD9380 Manual

Analog/hdmi dual-display interface
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FEATURES
Internal key storage for HDCP
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports HDCP 1.1
Digital audio interface
HDMI 1.1-compatible audio interface
www.BDTIC.com/ADI
S/PDIF (IEC90658-compatible) digital audio output
2
Multichannel I
S audio output (up to 8 channels)
APPLICATIONS
Advanced TVs
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9380 offers designers the flexibility of an analog
interface and high definition multimedia interface (HDMI)
receiver integrated on a single chip. Also included is support for
high bandwidth digital content protection (HDCP).
The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and FPD resolutions up to SXGA
(1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8 V and 3.3 V power supplies, analog input, and HSYNC .
Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
An on-chip PLL generates a pixel clock from HSYNC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Dual-Display Interface
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
R/G/B OR YPbPr
IN0
2:1
CLAMP
MUX
R/G/B OR YPbPr
IN1
HSYNC 0
2:1
MUX
HSYNC 1
HSYNC 0
2:1
SYNC
HSYNC 1
MUX
PROCESSING
2:1
SOGIN 0
AND
MUX
SOGIN 1
CLOCK
GENERATION
COAST
FILT
CKINV
CKEXT
SERIAL REGISTER
SCL
AND
SDA
POWER MANAGEMENT
DIGITAL INTERFACE
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
HDMI RECEIVER
Rx2–
RxC+
RxC–
RTERM
DDCSDA
HDCP
DDCSCL
Pixel clock output frequencies range from 12 MHz to 150 MHz.
PLL clock jitter is typically less than 700 ps p-p at 150 MHz.
The AD9380 also offers full sync processing for composite sync
and sync-on-green (SOG) applications.
The AD9380 contains an HDMI 1.1-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9380 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of the authentication during transmission, as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9380 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
Analog/HDMI
AD9380
R/G/B 8 × 3
A/D
OR YCbCr
2
DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REF
REFIN
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
R/G/B 8 × 3
OR YCbCr
2
DATACK
DE
HSYNC
VSYNC
S/PDIF
4
8-CHANNEL
2
I
SCLK
MCLK
LRCLK
HDCP KEYS
AD9380
Figure 1.
www.analog.com
DATACK
HSOUT
VSOUT
SOGOUT
DE
S

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Summary of Contents for Analog Devices AD9380

  • Page 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
  • Page 2 AD9380 TABLE OF CONTENTS Features ....................1 2-Wire Serial Register Map ............23 Applications..................1 2-Wire Serial Control Register DetailS........37 Functional Block Diagram .............. 1 Chip Identification ..............37 General Description ................. 1 PLL Divider Control ..............37 Specifications..................3 Clock Generator Control ............
  • Page 3 AD9380 SPECIFICATIONS ANALOG INTERFACE ELECTRICAL CHARACTERISTICS = 3.3 V, DV = PV = 1.8 V, ADC clock = maximum. Table 1. AD9380KSTZ-100 AD9380KSTZ-150 Parameter Temp Test Level Unit RESOLUTION Bits DC ACCURACY Differential Nonlinearity 25°C −0.6 +1.6/−1.0 ±0.7 +1.8/−1.0 Integral Nonlinearity 25°C...
  • Page 4 AD9380 AD9380KSTZ-100 AD9380KSTZ-150 Parameter Temp Test Level Unit POWER SUPPLY Supply Voltage Full 3.15 3.47 3.15 3.47 Supply Voltage Full Supply Voltage Full 3.47 3.47 Supply Voltage Full Supply Current (V 25°C Supply Current (DV 25°C DVDD Supply Current (V 25°C...
  • Page 5 AD9380 AD9380KSTZ-100 AD9380KSTZ-150 Test Parameter Level Conditions Unit POWER SUPPLY Supply Voltage 3.15 3.47 3.15 3.47 Supply Voltage Supply Voltage Supply Voltage Supply Current (Typical Pattern) Supply Current (Typical Pattern) 1, 4 Supply Current (Typical Pattern) DVDD Supply Current (Typical Pattern)
  • Page 6 AD9380 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress 3.6 V rating only; functional operation of the device at these or any 3.6 V...
  • Page 7 AD9380 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 GREEN 7 AIN0 GREEN 6 SOGIN 0 GREEN 5 GREEN 4 AIN1 GREEN 3 SOGIN 1 GREEN 2 GREEN 1 AIN0 GREEN 0 AD9380 AIN1 TOP VIEW (Not to Scale) BLUE 7...
  • Page 8 AD9380 Pin Type Pin No. Mnemonic Function Value OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB 2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB 12 to 19 BLUE [7:0]...
  • Page 9 AD9380 Table 6. Pin Function Descriptions Mnemonic Description INPUTS Analog Input for the Red Channel 0. AIN0 Analog Input for the Green Channel 0. AIN0 Analog Input for the Blue Channel 0. AIN0 Analog Input for the Red Channel 1.
  • Page 10 HSYNC from the filter, or the filtered HSYNC. See the Sync processing block diagram (see Figure 8 for pin connections). Note that besides slicing off SOG, the output from this pin is not processed on the AD9380. VSYNC separation is performed via the sync separator.
  • Page 11 This supplies power to the digital logic. Ground. The ground return for all circuitry on chip. It is recommended that the AD9380 be assembled on a single solid ground plane, with careful attention to ground current paths. The supplies should be sequenced such that V...
  • Page 12 All digital control inputs (HSYNC, VSYNC, and I C) on the preprocessed TTL or CMOS level signal. AD9380 operate to 3.3 V CMOS levels. In addition, all digital The HSYNC input includes a Schmitt trigger buffer for inputs, except the TMDS (HDMI/DVI) inputs, are 5 V tolerant.
  • Page 13 Clamp timing employs the AD9380 internal clamp timing The offset on the AD9380 can be adjusted automatically to a generator. The clamp placement register is programmed with specified target code. Using this option allows the user to set the...
  • Page 14 AD9380 clock generation circuit to minimize HSYNC and coast, a value of 1 is active high. The internal coast jitter. The clock jitter of the AD9380 is less than 13% of the total function is driven off the VSYNC signal, which is typically a...
  • Page 15 The power-down pin (Pin 81—polarity set by Register 0x26[3]) can drive the chip into four power-down The AD9380 uses the activity detect circuits, the active interface options. Bit 2 and Bit 1 of Register 0x26 control these four bits in the serial bus, the active interface override bits, the options.
  • Page 16 The known output polarity can be programmed either active high or active low (Register 0x24, There is a pipeline in the AD9380, which must be flushed Bit 7). Second, HSOUT is aligned with DATACK and the data before valid data becomes available.
  • Page 17 Sync Processing is to extract VSYNC from the composite sync signal, which can The inputs of the AD9380 sync processing section are come from either the sync slicer or the HSYNC input. The combinations of digital HSYNCs and VSYNCs, analog sync-on-...
  • Page 18 ±20% (160 ns to 240 ns). Because normal VSYNC and HSYNC pulse widths differ by a The sync separator on the AD9380 is simply an 8-bit digital factor of about 500 or more, 20% variability is not an issue.
  • Page 19 AD9380 HSYNC Filter and Regenerator timing, program a value (x) into Register 0x20. The resulting The HSYNC filter is used to eliminate any extraneous pulses filter window time is ±x times 25 ns either side of the from the HSYNC or SOGIN inputs, outputting a clean, low regenerated HSYNC leading edge.
  • Page 20 4:4:4 TO 4:2:2 FILTER FIELD 1 FIELD 0 FIELD 1 FIELD 0 The AD9380 contains a filter that allows it to convert a signal QUADRANT from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the HSIN maximum accuracy and fidelity of the original signal.
  • Page 21 Data contained in the audio infoframes, among other registers, The CSC matrix in the AD9380 consists of three identical define for the AD9380 HDMI receiver not only the type of processing channels. In each channel, three input values are audio, but the sample frequency. It also contains information multiplied by three separate coefficients.
  • Page 22 TIMING DIAGRAMS and HDMI transmissions and is located in read-only registers Figure 15 and Figure 16 show the operation of the AD9380.The R0x5A to R0xEE. In addition to this information, registers are output data clock signal is created so that its rising edge always provided to indicate that new information has been received.
  • Page 23 AD9380 2-WIRE SERIAL REGISTER MAP The AD9380 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. Control Register Map...
  • Page 24 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x12 Read/Write 1******* Input HSYNC Polarity 0 = active low. 1 = active high. *0****** HSYNC Polarity 0 = auto HSYNC polarity. Override 1 = manual HSYNC polarity. **1***** Input VSYNC Polarity 0 = active low.
  • Page 25 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x17 Read [3:0] ****0000 HSYNCs per VSYNC MSB of HSYNCs per VSYNC. 0x18 Read [7:0] 00000000 HSYNCs per VSYNC HSYNCs per VSYNC count. 0x19 Read/Write [7:0] 00001000 Clamp Placement Number of pixel clocks after trailing edge of HSYNC to begin clamp.
  • Page 26 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description *1****** PLL Sync Filter Enable Enables the PLL to use the filtered HSYNC rather than the raw HSYNC. This clips any bad HSYNCs, but does not regenerate missing pulses.
  • Page 27 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description ******1* Primary Output Enables primary output. Enable *******0 Enables secondary output (DDR 4:2:2 in Output Modes 1 and 2). Secondary Output Enable 0x26 Read/Write 0******* Output Three-State Three-state the outputs.
  • Page 28 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x2F Read *0****** TMDS Sync Detect Detects a TMDS DE. **0***** TMDS Active Detects a TMDS clock. ***0**** AV Mute Gives the status of AV mute based on general control packets.
  • Page 29 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x39 Read/Write [4:0] ***00000 CSC_Coeff_A3 MSB MSB, Register 0x3A. 0x3A Read/Write [7:0] 00000000 CSC_Coeff_A3 LSB CSC coefficient for equation: = (A1 × R ) + (A2 × G ) + (A3 × B ) + A4 = (B1 ×...
  • Page 30 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x56 Read/Write [7:0] 00001111 Test Must be written to 0x0F for proper operation. 0x57 Read/Write 0******* A/V Mute Override A1 overrides the AV mute value with Bit 6. *0****** AV Mute Value Sets AV mute value if override is enabled.
  • Page 31 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 1100 = 176.4 kHz. 0010 = 48k Hz. 1010 = 96 kHz. 1110 = 192 kHz. 0x62 Read [3:0] Word Length Word length. 0000 = not specified. 0100 = 16 bits.
  • Page 32 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description [3:0] Active Format Aspect R [3:0]. Ratio 1000 = same as picture aspect ratio. 1001 = 4:3 (center). 1010 = 16:9 (center). 1011 = 14:9 (center). 0x83 Read [1:0] Nonuniform Picture SC [1:0].
  • Page 33 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x0 = Refer to stream header. 0x1 = IEC60958 PCM. 0x2 = AC3. 0x3 = MPEG1 (Layer 1 and Layer 2). 0x4 = MP3 (MPEG1 Layer 3). 0x5 = MPEG2 (multichannel).
  • Page 34 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0x9E Read [7:0] VN6. 0x9F Read [6:0] New Data Flags New data flags (see 0x87). 0xA0 Read [7:0] VN7. 0xA1 Read [7:0] VN8. 0xA2 Read [7:0] Product Description Product Description Character 1 (PD1) in 7-bit ASCII code. This is...
  • Page 35 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0xBE Read [7:0] Reserved. 0xBF Read [6:0] New Data Flags New data flags (see 0x87). 0xC0 Read [7:0] Audio Content Audio content protection packet (ACP) type. Protection Packet 0x00 = Generic audio.
  • Page 36 AD9380 Read/Write Default Address or Read-Only Bits Value Register Name Description 0xE5 Read [7:0] ISRC2_PB8 ISRC2_PB8. 0xE6 Read [7:0] ISRC2_PB9 ISRC2_PB9. 0xE7 Read [6:0] New Data Flags New data flags (see Register 0x87). 0xE8 Read [7:0] ISRC2_PB10 ISRC2_PB10. 0xE9 Read...
  • Page 37 0x69, PLLDIVL = 0xDx) Bit[2] External Clock Enable The AD9380 updates the full divide ratio only when the LSBs This bit determines the source of the pixel clock. are changed. Writing to this register by itself does not trigger an Table 15.
  • Page 38 The power-up default is 0. 0x06—Bits[7:0] Green Channel Gain 0x0B—Bits[7-0] Green Channel Offset These bits control the PGA of the green channel. The AD9380 These eight bits are the green channel offset control. The offset can accommodate input signals with a full-scale range of control shifts the analog input, resulting in a change in bright- between 0.5 V p-p and 1.0 V p-p.
  • Page 39 AD9380 SYNC 0x12—Bits[6] HSYNC Polarity Override 0x0E—Bits[7:0] Sync Separator 0 = auto HSYNC polarity, 1 = manual HSYNC polarity. Manual HSYNC polarity is defined in Register 0x11, Bit 7. The power- Selects the maximum HSYNC pulse width for composite sync up default is 0.
  • Page 40 AD9380 0x15—Bit[6] HSYNC 1 Detection Bit 0x16—Bit[3] Coast Polarity This bit is used to indicate when activity is detected on the Indicates the polarity of the external coast signal. 0 = coast HSYNC 1 input pin. If HSYNC is held high or low, activity is polarity negative.
  • Page 41 AD9380 0x1B—Bit[4] Clamp During Coast 0x1D—Bits[7:0] Slew Limit This bit permits clamping to be disabled during coast because Limits the amount the offset can change by in a single update. video signals are generally not at a known back porch or The power-up default is 0x08.
  • Page 42 PLL feedback clock. These bits select the clock output on the DATACK pin. They The AD9380 then counts a number of pixel clocks equal to the include a 1/2× clock, a 2× clock, a 90° phase shifted clock, or value in this register.
  • Page 43 AD9380 0x26—Bit[7] Output Three-State 0x25—Bits[5:4] Output Drive Strength When enabled, this bit puts all outputs (except SOGOUT) in a These two bits select the drive strength for all the high speed high impedance state. 0 = normal outputs. 1 = all outputs digital outputs (except VSOUT, A0, and O/E field).
  • Page 44 AD9380 0x27—Bit[7] Auto Power-Down Enable 0x2B—Bits[7:0] Line Width LSBs This bit enables the chip to go into low power mode, or seek See the line width MSBs section. mode if no sync inputs are detected. 0 = auto power-down 0x2C—Bits[3:0] Screen Height MSBs disabled.
  • Page 45 AD9380 0x30—Bits[6] HDMI Content Encrypted 0x32—Bits[6] Macrovision PAL Enable This read-only bit is high when HDCP decryption is in use Tells the Macrovision detection engine to enter PAL mode when (content is protected). The signal goes low when HDCP is not set to 1.
  • Page 46 AD9380 COLOR SPACE CONVERSION 0x39—Bits[4:0] CSC A3 MSBs The default value for the 13-bit A3 is 0x0000. The default power up values for the color space converter coefficients (R0x35 through R0x4C) are set for ATSC RGB to 0x3A—Bits[7:0] CSC A3 LSBs YCbCr conversion.
  • Page 47 AD9380 0x58—Bits[6:4] MCLK PLL_N 0x5A—Bit[6:0] Packet Detect These bits control the division of the MCLK out of the PLL. This register indicates if a data packet in specific sections has been detected. These seven bits are updated if any specific Table 24.
  • Page 48 AD9380 0x85—Bits[3:0] Pixel Repeat 0x81—Bits[6:5] Y [1:0] This value indicates how many times the pixel was repeated. This register indicates whether data is RGB, 4:4:4, or 4:2:2. 0x0 = no repeats, sent once, 0x8 = 8 repeats, sent 9 times, and Table 28.
  • Page 49 AD9380 0x8E—Bits[7:0] Active Pixel End MSB 0x92—Bits[4:2] Sampling Frequency See Register 0x8D. 0x92—Bits[1:0] Ample Size 0x93—Bits[7:0] Max Bit Rate 0x8F—Bits[6:0] NDF For compressed audio only, when this value is multiplied by See Register 0x87. 8 kHz represents the maximum bit rate. A value of 0x08 in this 0x90—Bits[7:0] Audio Infoframe Version...
  • Page 50 AD9380 Table 39. Channel Number Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 – – – – – – – – –...
  • Page 51 AD9380 0xA3—Bits[7:0] PD2 0xBD—Bit[4] Field Repeat 0xA4—Bits[7:0] PD3 This bit defines whether the field is new or repeated. 0 = new 0xA5—Bits[7:0] PD4 field or picture. 1 = repeated field. 0xA6—Bits[7:0] PD5 0xBD—Bits[1:0] MPEG Frame 0xA7—Bits[6:0] New Data Flags These bits identify the frame as I, B, or P.
  • Page 52 AD9380 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xDD—Bits[7-0] ISRC2_PB1 0xCA—Bits[7:0] ISRC1_PB1 0xDE—Bits[7-0] ISRC2_PB2 0xCB—Bits[7:0] ISRC1_PB2 0xDF—Bits[6-0] New Data Flags 0xCC—Bits[7:0] ISRC1_PB3 See Register 0x87 for a description. 0xCD—Bits[7:0] ISRC1_PB4 0xE0—Bits[7:0] ISRC2_PB3 0xCE—Bits[7:0] ISRC1_PB5 0xE1—Bits[7:0] ISRC2_PB4 0xCF—Bits[6:0] New Data Flags 0xE2—Bits[7:0] ISRC2_PB5 See Register 0x87 for a description.
  • Page 53 • Data byte to read or write an acknowledge signal. • Stop signal Data are read from the control registers of the AD9380 in a • Acknowledge (ack) similar manner. Reading requires two data transfer operations: www.BDTIC.com/ADI When the serial interface is inactive (SCL and SDA are high) •...
  • Page 54 AD9380 SERIAL INTERFACE READ/WRITE EXAMPLES Read from one control register: • Start signal Write to one control register: • • Slave address byte (R/ W \ bit = low) Start signal • • Slave address byte (R/ W bit = low) Base address byte •...
  • Page 55 An example of a current loop is a power plane to and the input coupling capacitor can also be beneficial. AD9380 to digital output trace to digital data receiver to digital ground plane to analog ground plane. POWER SUPPLY BYPASSING It is recommended to bypass each power supply pin with a 0.1 μF capacitor.
  • Page 56 EMI, and reduce the current spikes inside the AD9380. If series resistors are used, place them as close as possible to the AD9380 pins (although try not to add vias or extra length to the output trace to move the resistors closer).
  • Page 57 AD9380 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 44. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9380) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff 3 Red/Cr Offset Address 0x35 0x36 0x37 0x38...
  • Page 58 AD9380 Table 48. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff Red/Cr Offset Address 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C Value 0x08 0x2D 0x18 0x93 0x1F 0x3F...
  • Page 59 AD9380 OUTLINE DIMENSIONS 16.00 1.60 MAX BSC SQ 0.75 0.60 0.45 PIN 1 14.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 VIEW A 0.17...
  • Page 60 NOTES www.BDTIC.com/ADI © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05688–0–10/05(0) Rev. 0 | Page 60 of 60...