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FEATURES
HDMI interface
Supports high bandwidth digital content protection
RGB to YCbCr 2-way color conversion
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
(HDCP 1.1)
Digital audio interface
HDMI 1.1-compatible audio interface
SPDIF (IEC90658-compatible) digital audio output
Multichannel I
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9398 offers a high definition multimedia interface
(HDMI) receiver integrated on a single chip. Also included is
support for high bandwidth digital content protection (HDCP).
The AD9398 contains a HDMI 1.0-compatible receiver and
supports all HDTV formats (up to 1080p) and display resolu-
tions up to SXGA (1280 × 1024 @ 75 Hz). The receiver features
an intrapair skew tolerance of up to one full clock cycle. With
the inclusion of HDCP, displays can now receive encrypted
video content. The AD9398 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and
renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9398 is
provided in a space-saving 100-lead, surface-mount, Pb-free,
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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2
S audio output (up to 8 channels)
HDMI™ Display Interface
FUNCTIONAL BLOCK DIAGRAM
SCL
SERIAL REGISTER
AND
SDA
POWER MANAGEMENT
Rx0+
Rx0–
Rx1+
Rx1–
HDMI
Rx2+
RECEIVER
Rx2–
RxC+
RxC–
RTERM
MCL
MDA
HDCP
DDCSCL
DDCSDA
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9398
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
R/G/B 8 × 3
OR YCbCr
2
DATACK
HSYNC
VSYNC
DE
DE
S/PDIF OUT
8-CHANNEL
2
I
S
MCLK
LRCLK
AD9398
www.analog.com
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Table of Contents
Related Manuals for Analog Devices AD9398
Summary of Contents for Analog Devices AD9398
-
Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. -
Page 2: Table Of Contents
AD9398 TABLE OF CONTENTS Features ....................1 4:4:4 to 4:2:2 Filter ..............11 Applications..................1 Audio PLL Setup................. 12 Functional Block Diagram .............. 1 Audio Board Level Muting............13 General Description ................. 1 Output Data Formats..............13 Specifications..................3 2-Wire Serial Register Map ............14 Electrical Characteristics............. -
Page 3: Specifications
AD9398 SPECIFICATIONS ELECTRICAL CHARACTERISTICS = 3.3 V, DV = PV = 1.8 V, ADC clock = maximum. Table 1. AD9398KSTZ-100 AD9398KSTZ-150 Parameter Temp Test Level Unit DIGITAL INPUTS (5 V TOLERANT) Input Voltage, High (V Full Input Voltage, Low (V... - Page 4 AD9398 AD9398KSTZ-100 AD9398KSTZ-150 Parameter Test Level Conditions Unit POWER SUPPLY Supply Voltage 3.15 3.47 3.15 3.47 Supply Voltage Supply Voltage Supply Voltage Supply Current (Typical Pattern) Supply Current (Typical Pattern) Supply Current (Typical Pattern) DVDD Supply Current (Typical Pattern) PVDD...
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Page 5: Absolute Maximum Ratings
AD9398 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress 3.6 V rating only; functional operation of the device at these or any 3.6 V... -
Page 6: Pin Configuration And Function Descriptions
AD9398 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN 0 AD9398 TOP VIEW (Not to Scale) BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3... - Page 7 Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4]. Data Enable that defines valid video. Can be received in the signal or generated by the AD9398. Rev. 0 | Page 7 of 44 Downloaded from Elcodis.com...
- Page 8 AD9398 Mnemonic Description RTERM RTERM is the termination resistor used to drive the AD9398 internally to a precise 50 Ω termination for TMDS lines. This should be a 500 Ω 1% tolerance resistor. AUDIO DATA OUTPUT S/PDIF Sony/Philips Digital Interface. Supports digital audio from 32 kbps to 192 kbps.
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Page 9: Design Guide
Table 7 summarizes Included in the output formatting is a color space converter how the AD9398 determines the power mode to use and which (CSC), which accommodates any input color space and can circuitry is powered on/off in each of these modes. The power- output any color space. -
Page 10: Timing
O/E FIELD DE GENERATOR EVEN FIELD The AD9398 has an on-board generator for DE, for start of Figure 4. VSYNC Filter—Even active video (SAV), and for end of active video (EAV), all of which are necessary for describing the complete data stream for a BT656-compatible output. -
Page 11: 4:4:4 To 4:2:2 Filter
AD9398 4:4:4 TO 4:2:2 FILTER The AD9398 contains a filter that allows it to convert a signal One of the three channels is represented in Figure 6. In each from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the processing channel, the three inputs are multiplied by three maximum accuracy and fidelity of the original signal. -
Page 12: Audio Pll Setup
Data contained in the audio infoframes, among other registers, characteristics are determined by the loop filter design, the PLL define for the AD9398 HDMI receiver not only the type of charge pump current, and the VCO range setting. The loop audio, but the sampling frequency (f ). -
Page 13: Audio Board Level Muting
Audio coding OUTPUT DATA FORMATS • Audio sampling frequency The AD9398 supports 4:4:4, 4:2:2, double data rate (DDR), and • Speaker placement BT656 output formats. Register 0x25[3:0] controls the output mode. These modes and the pin mapping are listed in Table 10. -
Page 14: 2-Wire Serial Register Map
AD9398 2-WIRE SERIAL REGISTER MAP The AD9398 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11. Control Register Map... - Page 15 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description **1***** DE Output Polarity Output DE polarity. 0 = active low out. 1 = active high out. ***1**** Field Output Polarity Output field polarity. 0 = active low out.
- Page 16 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description ***0**** BT656 EN Enables EAV/SAV codes to be inserted into the video output data. ****0*** Force DE Generation Allows use of the internal DE generator in DVI mode.
- Page 17 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description **0***** Low Freq Mode Sets audio PLL to low frequency mode. Low frequency mode should only be set for pixel clocks <80 MHz. ***0**** Low Freq Override Allows the previous bit to be used to set low frequency mode rather than the internal auto-detect.
- Page 18 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description 0x44 Read/Write [7:0] 10010010 CSC_Coeff_B4 LSB CSC coefficient for equation: = (A1 × R ) + (A2 × G ) + (A3 × B ) + A4 = (B1 ×...
- Page 19 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description ACP packets. ISRC1 packets. ISRC2 packets. 0x5B Read HDMI Mode 0 = DVI, 1 = HDMI. 0x5E Read [7:6] Channel Status Mode = 00. All others are reserved.
- Page 20 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description 0x7F Read [7:0] N [7:0] AVI Infoframe 0x80 Read [7:0] AVI Infoframe Version 0x81 Read [6:5] Y [1:0] Indicates RGB, 4:2:2, or 4:4:4. 00 = RGB. 01 = YCbCr 4:2:2.
- Page 21 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description 0x87 Read [6:0] New Data Flags New data flags. These 8 bits are updated if any specific data changes. Normal (no NDFs) is 0x00. When any NDF register is read, all bits reset to 0x00.
- Page 22 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description 110 = 176.4 kHz. 111 = 192 kHz. [1:0] Sample Size SS [1:0]. Sample size. 00 = refer to stream header. 01 = 16-bit. 10 = 20-bit.
- Page 23 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description 0xAF Read [6:0] New Data Flags New data flags (see 0x87). 0xB0 Read [7:0] PD13 PD13. 0xB1 Read [7:0] PD14 PD14. 0xB2 Read [7:0] PD15 PD15. 0xB3...
- Page 24 AD9398 Read/Write or Read Default Hex Address Only Bits Value Register Name Description 0xC8 ISRC1 Continued International standard recording code (ISRC1). continued. This indicates an ISRC2 packet is being transmitted. Read ISRC1 Valid 0 = ISRC1 status bits and PBs not valid.
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Page 25: 2-Wire Serial Control Register Details
AD9398 2-WIRE SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x12—Bit[4] VSYNC Polarity Override 0x00—Bits[7:0] Chip Revision 0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual VSYNC polarity is defined in Register 0x11, Bit 5. The power- An 8-bit value that reflects the current chip revision. - Page 26 PLL feedback clock. drive strength results in faster rise/fall times and in general The AD9398 then counts a number of pixel clocks equal to the makes it easier to capture data. Lower drive strength results in value in this register.
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Page 27: Bt656 Generation
AD9398 0x27—Bit[5] MCLK External Enable 0x26—Bit[7] Output Three-State This bit enables the MCLK to be supplied externally. If an When enabled, this bit puts all outputs (except SOGOUT) in a external MCLK is used, then it must be locked to the video high impedance state. -
Page 28: Macrovision
AD9398 0x2E—Bit[7] Ctrl Enable 0x30—Bit[5] DVI HSYNC Polarity When set, this bit allows Ctrl [3:0] signals decoded from the This read-only bit indicates the polarity of the DVI HSYNC. DVI to be output on the I S data pins. 0 = I S signals on I 0 = DVI HSYNC polarity is low active. -
Page 29: Color Space Conversion
AD9398 0x33—Bit[7] Macrovision Detect Mode 0x35—Bits[6:5] Color Space Converter Mode 0 = standard definition. 1 = progressive scan mode. These two bits set the fixed-point position of the CSC coefficients, including the A4, B4, and C4 offsets. 0x33—Bit[6] Macrovision Settings Override Table 17. - Page 30 AD9398 0x40—Bits[7:0] CSC B2 LSBs 0x58—Bits[2:0] MCLK f 0x41—Bits[4:0] CSC B3 MSBs These bits control the multiple of 128 f used for MCLK out. The default value for the 13-bit B3 is 0x1E89. Table 19. MCLK f _N [2:0] Multiple 0x42—Bits[7:0] CSC B3 LSBs...
- Page 31 AD9398 0x5E—Bits[7:6] Channel Status Mode 0x81—Bits[1:0] Scan Information Table 24. 0x5E—Bits[5:3] PCM Audio Data S [1:0] Scan Type 0x5E—Bit[2] Copyright Information No information 0x5E—Bit[1] Linear PCM Identification Overscanned (television) 0x5E—Bit[0] Use of Channel Status Block Underscanned (computer) 0x5F—Bits[7:0] Channel Status Category Code 0x60—Bits[7:4] Channel Number...
- Page 32 AD9398 0x91—Bits[7:4] Audio Coding Type 0x87—Bit[6:0] New Data Flags (NDF) These bits identify the audio coding so that the receiver may This register indicates whether data in specific sections has process audio properly. changed. In the address space from 0x80 to 0xFF, each register Table 30.
- Page 33 AD9398 Table 33. Channel Number Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 – – – – – – – – –...
- Page 34 AD9398 0xA3—Bits[7:0] PD2 0xBD—Bit[4] Field Repeat 0xA4—Bits[7:0] PD3 This defines whether the field is new or repeated. 0 = new field 0xA5—Bits[7:0] PD4 or picture. 1 = repeated field. 0xA6—Bits[7:0] PD5 0xBD—Bits[1:0] MPEG Frame 0xA7—Bits[6:0] New Data Flags This identifies the frame as I, B, or P.
- Page 35 AD9398 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xDD—Bits[7:0] ISRC2_PB1 0xCA—Bits[7:0] ISRC1_PB1 0xDE—Bits[7:0] ISRC2_PB2 0xCB—Bits[7:0] ISRC1_PB2 0xDF—Bits[6:0] New Data Flags 0xCC—Bits[7:0] ISRC1_PB3 See Register 0x87 for a description. 0xCD—Bits[7:0] ISRC1_PB4 0xE0—Bits[7:0] ISRC2_PB3 0xCE—Bits[7:0] ISRC1_PB5 0xE1—Bits[7:0] ISRC2_PB4 0xCF—Bits[6:0] New Data Flags 0xE2—Bits[7:0] ISRC2_PB5 See Register 0x87 for a description.
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Page 36: 2-Wire Serial Control Port
SCL and SDA are pulled high by external pull-up resistors. To write data to specific control registers of the AD9398, the 8- Data received or transmitted on the SDA line must be stable for bit address of the control register of interest must be written the duration of the positive-going SCL pulse. -
Page 37: Serial Interface Read/Write Examples
AD9398 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: Read from one control register: • • Start signal Start signal • Slave address byte (R/ W bit = low) • Slave address byte (R/ W bit = low) •... -
Page 38: Pcb Layout Recommendations
If series resistors are used, place them as close as possible to the Placing a via underneath the capacitor pads down to the power AD9398 pins (although try not to add vias or extra length to the plane is generally the best approach. -
Page 39: Color Space Converter (Csc) Common Settings
AD9398 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 38. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9398) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff 3 Red/Cr Offset Address 0x35 0x36 0x37 0x38... - Page 40 AD9398 Table 42. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff Red/Cr Offset Address 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C Value 0x08 0x2D 0x18 0x93 0x1F 0x3F...
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Page 41: Outline Dimensions
AD9398 OUTLINE DIMENSIONS 16.00 1.60 MAX BSC SQ 0.75 0.60 0.45 PIN 1 14.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 VIEW A 0.17... - Page 42 AD9398 NOTES Rev. 0 | Page 42 of 44 Downloaded from Elcodis.com electronic components distributor...
- Page 43 AD9398 NOTES Rev. 0 | Page 43 of 44 Downloaded from Elcodis.com electronic components distributor...
- Page 44 AD9398 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05678-0-10/05(0) Rev. 0 | Page 44 of 44 Downloaded from Elcodis.com electronic components distributor...
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