Analog Devices AD9380 Manual page 23

2-WIRE SERIAL REGISTER MAP
The AD9380 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 12. Control Register Map
Hex Read/Write
Address or Read-Only
0x00 Read
0x01 Read/Write
0x02 Read/Write
0x03 Read/Write
0x04 Read/Write
0x05 Read/Write
0x06 Read/Write
0x07 Read/Write
0x08 Read/Write
0x09 Read/Write
0x0A Read/Write
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0x0B Read/Write
0x0C Read/Write
0x0D Read/Write
0x0E Read/Write
0x0F Read/Write
0x10 Read/Write
0x11 Read/Write
Default
Value
Bits Register Name
[7:0] 00000000 Chip Revision
[7:0] 01101001 PLL Divider MSB
[7:4] 1101**** PLL Divider
[7:6] 01****** VCO Range
[5:3] **001*** Charge Pump
[2] *****0** External Clock Enable
[7:3] 10000*** Phase Adjust
[7:0] 10000000 Red Gain
[7:0] 10000000 Green Gain
[7:0] 10000000 Blue Gain
[7:0] 00000000 Red Offset Adjust
[7:0] 10000000 Red Offset
[7:0] 00000000 Green Offset Adjust
[7:0] 10000000 Green Offset
[7:0] 00000000 Blue Offset Adjust
[7:0] 10000000 Blue Offset
[7:0] 00100000 Sync Separator
Threshold
[7:2] 010000** SOG Comparator
Threshold Enter
[7:2] 010000** SOG Comparator
Threshold Exit
[7] 0******* HSYNC Source
[6] *0****** HSYNC Source
Override
[5] **0***** VSYNC Source
[4] ***0**** VSYNC Source
Override
[3] ****0*** Channel Select
[2] *****0** Channel Select
Override
[1] ******0* Interface Select
[0] *******0 Interface Override
Description
Chip revision ID.
PLL feedback divider value MSB.
PLL feedback divider value.
VCO range.
Charge pump current control for PLL.
Selects the external clock input rather than the internal PLL
clock.
Selects the clock phase to use for the ADC clock.
Controls the gain of the red channel PGA. 0 = low gain,
255 = high gain.
Controls the gain of the green channel PGA. 0 = low gain,
255 = high gain.
Controls the gain of the blue channel PGA. 0 = low gain,
255 = high gain.
User adjustment of auto-offset. Allows user control of
brightness.
Red offset/target code. 0 = small offset, 255 = large offset.
User adjustment of auto-offset. Allows user control of
brightness.
Green offset/target code. 0 = small offset, 255 = large offset.
User adjustment of auto-offset. Allows user control of
brightness.
Blue offset/target code. 0 = small offset, 255 = large offset.
Selects the maximum HSYNC pulse width for composite sync
separation.
The enter level for the SOG slicer. Must be less than or equal to
the exit level.
The exit level for the SOG slicer. Must be greater than or equal to
the enter level.
0 = HSYNC.
1 = SOG.
0 = auto HSYNC source.
1 = manual HSYNC source.
0 = VSYNC.
1 = VSYNC from SOG.
0 = auto HSYNC source.
1 = manual HSYNC source.
0 = Channel 0.
1 = Channel 1.
0 = autochannel select.
1 = manual channel select.
0 = analog interface.
1 = digital interface.
0 = auto-interface select.
1 = manual interface select.
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AD9380