Analog Devices AD9380 Manual page 22

AD9380
This information is the fundamental difference between DVI
and HDMI transmissions and is located in read-only registers
R0x5A to R0xEE. In addition to this information, registers are
provided to indicate that new information has been received.
Registers with addresses ending in 0xX7 or 0xXF, beginning at
R0x87 contain the new data flag (NDF) information. These
registers contain the same information and all are reset once
any of them are read. Although there is no external interrupt
signal, the user easily can read any of these registers to see if
there is new information to be processed.
DATAIN
HSIN
DATACK
DATAOUT
HSOUT
DATAIN
HSIN
DATACK
YOUT
CB/CROUT
HSOUT
Table 11.
Port Red
Bit 7 6 5
4:4:4 Red/Cr [7:0]
4:2:2 CbCr [7:0]
↑
4:4:4 DDR DDR G [3:0]
↓
DDR R [7:0]
4:2:2 to 12 CbCR [11:0]
Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.
1
P0 P1 P2 P3
2 CLOCK CYCLE DELAYS
P0 P1 P2 P3
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2 CLOCK CYCLE DELAYS
NOTES:
1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAYS BETWEEN HSOUT AND DATAOUT.
Figure 16. YCrCb ADC Timing
4 3 2 1 0
↑
1
DDR B [7:4]
1
TIMING DIAGRAMS
Figure 15 and Figure 16 show the operation of the AD9380.The
output data clock signal is created so that its rising edge always
occurs between data transitions and can be used to latch the
output data externally. There is a pipeline in the AD9380 that
must be flushed before valid data becomes available. This
means six data sets are presented before valid data is available.
P4 P5 P6 P7 P8
8 CLOCK CYCLE DELAYS
Figure 15. RGB ADC Timing
P4 P5 P6 P7
Green
7 6 5 4 3
Green/Y [7:0]
Y [7:0]
↑
DDR B [3:0] DDR 4:2:2
↓
DDR G [7:4] DDR 4:2:2
Y [11:0]
Rev. 0 | Page 22 of 60
P9 P10 P11
P0 P1 P2
P3
P8 P9 P10 P11
8 CLOCK CYCLE DELAYS
Y0 Y1 Y2 Y3
B0 R0 B2 R2
Blue
2 1 0 7 6 5
Blue/Cb [7:0]
DDR 4:2:2
↑
CbCr [11:0]
↓
Y,Y [11:0]
4 3 2 1 0
↑ ↓
CbCr Y, Y