Analog Devices AD9380 Manual page 11

Mnemonic Description
1
POWER SUPPLY
V (3.3 V) Analog Power Supply.
D
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
V (1.8 V to 3.3 V)
Digital Output Power Supply.
DD
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the V
the sensitive analog circuitry can be minimized. If the AD9380 is interfacing with lower voltage logic, V
connected to a lower supply voltage (as low as 1.8 V) for compatibility.
PV (1.8 V) Clock Generator Power Supply.
DD
The most sensitive portion of the AD9380 is the clock generation circuitry. These pins provide power to the clock
PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to
these pins.
DV (1.8 V) Digital Input Power Supply.
DD
This supplies power to the digital logic.
GND Ground.
The ground return for all circuitry on chip. It is recommended that the AD9380 be assembled on a single solid
ground plane, with careful attention to ground current paths.
1 The supplies should be sequenced such that V
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and V are never less than 300 mV below DV
D DD
Rev. 0 | Page 11 of 60
pins, so output noise transferred into
D
. At no time should DV be more than 300 mV greater than V
DD DD
AD9380
may be
DD
or V .
D DD