Analog Devices AD9380 Manual page 8

AD9380
Pin Type
OUTPUTS
REFERENCES
POWER SUPPLY
CONTROL
HDCP
AUDIO DATA OUTPUTS
DIGITAL VIDEO DATA
DIGITAL VIDEO CLOCK
INPUTS
DATA ENABLE
RTERM
Pin No. Mnemonic
92 to 99 RED [7:0]
2 to 9 GREEN [7:0]
12 to 19 BLUE [7:0]
89 DATACK
87 HSOUT
85 VSOUT
86 SOGOUT
84 O/E FIELD
57 FILT
80, 76, 72, V
D
67, 45, 33
100, 90, 10 V
DD
59, 56, 54 PV
DD
48, 32, 30 DV
DD
GND
82 SCL
83 SDA
49 DDCSCL
50 DDCSDA
51 PU2
52 PU1
28 S/PDIF
2
27 I S0
2
26 I S1
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2
25 I S2
2
24 I S3
20 MCLKIN
21 MCLKOUT
22 SCLK
23 LRCLK
34 Rx0−
35 Rx0+
37 Rx1−
38 Rx1+
40 Rx2−
41 Rx2+
43 RxC+
44 RxC−
88 DE
46 RTERM
Function
Outputs of Red Converter, Bit 7 is MSB
Outputs of Green Converter, Bit 7 is MSB
Outputs of Blue Converter, Bit 7 is MSB
Data Output Clock
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
SOG Slicer Output
Odd/Even Field Output
Connection for External Filter Components For PLL
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data Clock
Serial Port Data I/O
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
Should be tied to 3.3 V through a 10 kΩ resistor
Should be tied to 3.3 V through a 10 kΩ resistor
S/PDIF Digital Audio Output
2
I S Audio (Channel 1, Channel 2)
2
I S Audio (Channel 3, Channel 4)
2
I S Audio (Channel 5, Channel 6)
2
I S Audio (Channel 7, Channel 8)
External Reference Audio Clock In
Audio Master Clock Output
Audio Serial Clock Output
Data Output Clock for Left And Right Audio Channels
Digital Input Channel 0 Complement
Digital Input Channel 0 True
Digital Input Channel 1 Complement
Digital Input Channel 1 True
Digital Input Channel 2 Complement
Digital Input Channel 2 True
Digital Data Clock True
Digital Data Clock Complement
Data Enable
Sets Internal Termination Resistance
Rev. 0 | Page 8 of 60
Value
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
3.3 V
1.8 V to 3.3 V
1.8 V
1.8 V
0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
3.3 V CMOS
500 Ω