Analog Devices AD9380 Manual page 26

AD9380
Hex Read/Write
Address or Read-Only
0x22 Read/Write
0x23 Read/Write
0x24 Read/Write
0x25 Read/Write
Default
Bits Value Register Name
[6] *1****** PLL Sync Filter Enable
[5] **0***** VSYNC Filter Enable
[4] ***0**** VSYNC Duration
Enable
[3] **** 1*** Auto-Offset Clamp
Mode
[2] **** *1** Auto-Offset Clamp
Length
[7:0] 4 VSYNC Duration
[7:0] 32 HSYNC Duration
[7] 1******* HSYNC Output
Polarity
[6] *1****** VSYNC Output
Polarity
www.BDTIC.com/ADI
[5] **1***** DE Output Polarity
[4] ***1**** Field Output Polarity
[3] ****1*** SOG Output Polarity
[2:1] *****11* SOG Output Select
[0] *******0 Output CLK Invert
[7:6] 01****** Output CLK Select
[5:4] **11**** Output Drive
Strength
[3:2] ****00** Output Mode
Description
Enables the PLL to use the filtered HSYNC rather than the raw
HSYNC. This clips any bad HSYNCs, but does not regenerate
missing pulses.
Enables the VSYNC filter. The VSYNC filter gives a predictable
HSYNC/VSYNC timing relationship but clips one HSYNC period
off the leading edge of VSYNC.
Enables the VSYNC duration block. This block can be used if
necessary to restore the duration of a filtered VSYNC.
0 = auto-offset measures code during clamp.
1 = auto-offset measures code (10 or 16) clock cycles after end
of clamp for 6 clock cycles.
Sets delay after end of clamp for auto-offset clamp mode = 1.
0 = delay is 10 clock cycles.
1 = delay is 16 clock cycles.
VSYNC duration.
HSYNC duration. Sets the duration of the output HSYNC in pixel
clocks.
Output HSYNC polarity (both DVI and analog), 0 = active low
out.
1 = active high out.
Output VSYNC polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output DE polarity (both DVI and analog) .
0 = active low out.
1 = active high out.
Output field polarity (both DVI and analog).
0 = active low out.
1 = active high out.
Output SOG polarity (analog only).
0 = active low out.
1 = active high out.
Selects signal present on SOG output.
00 = SOG0 or SOG1.
01 = Raw HSYNC0 or Raw HSYNC1.
10 = regenerated sync.
11 = HSYNC to PLL.
0 = don't invert clock out.
1 = invert clock out.
Select which clock to use on output pin. 1× CLK is divided down
from TMDS clock input when pixel repetition is in use.
00 = ½× CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1× CLK.
Set the drive strength of the outputs.
00 = lowest, 11 = highest.
Selects which pins the data comes out on.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.
11 = 12-bit 4:2:2 (HDMI can have 12-bit 4:2:2 data).
Rev. 0 | Page 26 of 60