Analog Devices AD9381 Manual

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FEATURES

Internal HDCP keys

HDMI interface

Supports high bandwidth digital content protection

RGB to YCbCr 2-way color conversion

1.8 V/3.3 V power supply

100-lead Pb-free LQFP

RGB and YCbCr output formats

Digital video interface

HDMI 1.1, DVI 1.0

150 MHz HDMI receiver

Supports high bandwidth digital content protection

(HDCP 1.1)

Digital audio interface

HDMI 1.1-compatible audio interface

S/PDIF (IEC90658-compatible) digital audio output

Multichannel I

S audio output (up to 8 channels)

APPLICATIONS

Advanced TVs

HDTVs

Projectors

LCD monitors

GENERAL DESCRIPTION

The AD9381 offers a high definition multimedia interface

(HDMI) receiver integrated on a single chip. Also included is

support for high bandwidth digital content protection (HDCP)

via an internal key storage.

The AD9381 contains an HDMI 1.0-compatible receiver and

supports all HDTV formats (up to 1080p) and display

resolutions up to SXGA (1280×1024 @ 75 Hz). The receiver

features an intrapair skew tolerance of up to one full clock cycle.

With the inclusion of HDCP, displays may now receive

encrypted video content. The AD9381 allows for authentication

of a video receiver, decryption of encoded data at the receiver,

and renewability of that authentication during transmission as

specified by the HDCP 1.1 protocol.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

HDMI™ Display Interface

FUNCTIONAL BLOCK DIAGRAM

SCL

SERIAL REGISTER

AND

SDA

POWER MANAGEMENT

Rx0+

Rx0–

Rx1+

Rx1–

HDMI RECEIVER

Rx2+

Rx2–

RxC+

RxC–

RTERM

DDCSDA

HDCP

DDCSCL

Fabricated in an advanced CMOS process, the AD9381 is

provided in a space-saving, 100-lead, surface-mount, Pb-free

plastic LQFP and is specified over the 0°C to 70°C temperature

range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

AD9381

R/G/B 8 × 3

YCbCr (4:2:2

OR 4:4:4)

R/G/B 8 × 3

OR YCbCr

DATACK

HSYNC

VSYNC

S/PDIF

8-CHANNEL

MCLK

LRCLK

HDCP KEYS

AD9381

Figure 1.

www.analog.com

DATACK

HSOUT

VSOUT

Table of Contents

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Summary of Contents for Analog Devices AD9381

Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Page 2: Table Of Contents
AD9381 TABLE OF CONTENTS Features ....................1 4:4:4 to 4:2:2 Filter ..............11 Applications..................1 Audio PLL Setup................. 12 Functional Block Diagram .............. 1 Audio Board Level Muting............13 General Description ................. 1 Output Data Formats..............13 Specifications..................3 2-Wire Serial Register Map ............14 Electrical Characteristics.............
Page 3: Specifications
AD9381 SPECIFICATIONS ELECTRICAL CHARACTERISTICS = 3.3 V, DV = PV = 1.8 V, ADC clock = maximum. Table 1. AD9381KSTZ-100 AD9381KSTZ-150 Parameter Temp Test Level Unit DIGITAL INPUTS (5 V Tolerant) Input Voltage, High (V Full Input Voltage, Low (V...
Page 4 AD9381 AD9381KSTZ-100 AD9381KSTZ-150 Parameter Test Level Conditions Unit Supply Current (Typical DVDD 1, 4 Pattern) Supply Current (Typical PVDD Pattern) Power-Down Supply Current (I AC SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (T Channel to Channel Differential Clock Input Skew (T...
Page 5: Absolute Maximum Ratings
AD9381 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress 3.6 V rating only; functional operation of the device at these or any 3.6 V...
Page 6: Pin Configuration And Function Descriptions
AD9381 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN 0 AD9381 TOP VIEW (Not to Scale) BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3...
Page 7 AD9381 Pin Type Pin No. Mnemonic Function Value REFERENCES FILT Connection for External Filter Components for Audio PLL POWER SUPPLY 80, 76, 72, 67, Analog Power Supply and DVI Terminators 3.3 V 45, 33 100, 90, 10 Output Power Supply 1.8 V to 3.3 V...
Page 8 This supplies power to the digital logic. Ground. The ground return for all circuitry on chip. It is recommended that the AD9381 be assembled on a single solid ground plane, with careful attention to ground current paths. The supplies should be sequenced such that V...
Page 9: Design Guide
DESIGN GUIDE GENERAL DESCRIPTION SERIAL CONTROL PORT The AD9381 is a fully integrated solution for receiving DVI/ The serial control port is designed for 3.3 V logic. However, it is HDMI signals and is capable of decoding HDCP-encrypted tolerant of 5 V logic signals.
Page 10: Timing
O/E FIELD DE GENERATOR EVEN FIELD The AD9381 has an onboard generator for DE, for start of Figure 4. active video (SAV) and for end of active video (EAV), all of which is necessary for describing the complete data stream for a BT656-compatible output.
Page 11: 4:4:4 To 4:2:2 Filter
One of the three channels is represented in Figure 6. In each processing channel, the three inputs are multiplied by three The AD9381 contains a filter that allows it to convert a signal separate coefficients marked a1, a2, and a3. These coefficients...
Page 12: Audio Pll Setup
Data contained in the audio infoframes, among other registers, In order to provide the most flexibility in configuring the audio define for the AD9381 HDMI receiver not only the type of sampling clock, an additional PLL is employed. The PLL audio, but the sampling frequency (f ).
Page 13: Audio Board Level Muting
AD9381 AUDIO BOARD LEVEL MUTING This information is the fundamental difference between DVI and HDMI transmissions and is located in read-only registers The audio can be muted through the infoframes or locally R0x5A to R0xEE. In addition to this information, registers are via the serial bus registers.
Page 14: 2-Wire Serial Register Map
AD9381 2-WIRE SERIAL REGISTER MAP The AD9381 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11. Control Register Map...
Page 15 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description ***1**** Field Output Polarity Output field polarity. 0 = active low out. 1 = active high out. *******0 Output CLK Invert 0 = don’t invert clock out. 1 = invert clock out.
Page 16 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description [2:0] *****000 Interlace Offset Sets the difference (in HSYNCs) in field length between Field 0 and Field 1. 0x28 Read/Write [7:2] 011000** VS Delay Sets the delay (in lines) from the VSYNC leading edge to the start of active video.
Page 17 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description ***0**** Low Freq Override Allows the previous bit to be used to set low frequency mode rather than the internal auto- detect. ****0*** Up Conversion Mode 0 = repeat Cr and Cb values.
Page 18 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description 0x43 Read/Write [4:0] ***00010 CSC_Coeff_B4 MSB MSB, Register 0x44. 0x44 Read/Write [7:0] 10010010 CSC_Coeff_B4 LSB CSC coefficient for equation: = (A1 × R ) + (A2 × G ) + (A3 ×...
Page 19 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description 0x5A Read [6:0] Packet Detected These 7 bits are updated if any specific packet has been received since last reset or loss of clock detect. Normal is 0x00.
Page 20 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description 0x62 Read [3:0] Word Length Word length. 0000 not specified. 0100 = 16 bits. 0011 = 17 bits. 0010 = 18 bits. 0001 = 19 bits. 0101 = 20 bits.
Page 21 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description [3:0] Active Format Aspect R [3:0]. Ratio 1000 = same as picture aspect ratio. 1001 = 4:3 (center). 1010 = 16:9 (center). 1011 = 14:9 (center). 0x83 Read...
Page 22 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description 0x90 Read [7:0] Audio Infoframe Version 0x91 Read [7:4] Audio Coding Type CT [3:0]. Audio coding type. 0x00 = refer to stream header. 0x01 = IEC60958 PCM. 0x02 = AC3.
Page 23 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description Source Product Description (SPD) Infoframe 0x98 Read [7:0] Source Product Description (SPD) Infoframe Version 0x99 Read [7:0] Vendor Name Vendor name character 1 (VN1) 7-bit ASCII code. Character 1 The first character in 8 that is the name of the company that appears on the product.
Page 24 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description MPEG Source Infoframe 0xB8 Read [7:0] MPEG Source Infoframe Version 0xB9 Read [7:0] MB(0) MB [0] (Lower byte of MPEG bit rate: Hz). The lower 8 bits of 32 bits (4 bytes) that specify the MPEG bit rate in Hz.
Page 25 AD9381 Read/Write Address or Read Only Bits Default Value Register Name Description 0xD2 Read [7:0] ISRC1_PB8 ISRC1_PB8. 0xD3 Read [7:0] ISRC1_PB9 ISRC1_PB9. 0xD4 Read [7:0] ISRC1_PB10 ISRC1_PB10. 0xD5 Read [7:0] ISRC1_PB11 ISRC1_PB11. 0xD6 Read [7:0] ISRC1_PB12 ISRC1_PB12. 0xD7 Read [6:0] New data flags (see 0x87).
Page 26: 2-Wire Serial Control Register Details
AD9381 2-WIRE SERIAL CONTROL REGISTER DETAILS 0x12—Bit[4] VSYNC Polarity Override CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision 0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual VSYNC polarity is defined in Register 0x11, Bit 5. The power- An 8-bit value that reflects the current chip revision.
Page 27 PLL feedback clock. Output Drive Result The AD9381 then counts a number of pixel clocks equal to the Low output drive strength value in this register. This triggers the trailing edge of the Medium low output drive strength HSYNC output, which is also phase-adjusted.
Page 28: Bt656 Generation
AD9381 0x27—Bit[5] MCLK External Enable 0x26—Bit[7] Output Three-State This bit enables the MCLK to be supplied externally. If an When enabled, this bit puts all outputs (except SOGOUT) external MCLK is used, then it must be locked to the video in a high impedance state.
Page 29: Macrovision
AD9381 0x2E—Bit[7] Ctrl Enable 0x30—Bit[5] DVI HSYNC Polarity When set, this bit allows Ctrl [3:0] signals decoded from the This read-only bit indicates the polarity of the DVI HSYNC. DVI to be output on the I S data pins. 0 = I S signals on I 0 = DVI HSYNC polarity is low active.
Page 30: Color Space Conversion
AD9381 0x33—Bit[7] Macrovision Detect Mode 0x35—Bits[6:5] Color Space Converter Mode 0 = standard definition. 1 = progressive scan mode. These two bits set the fixed point position of the CSC coefficients, including the A4, B4, and C4 offsets. 0x33—Bit[6] Macrovision Settings Override Table 17.
Page 31 AD9381 0x40—Bits[7:0] CSC B2 LSBs 0x58—Bits[2:0] MCLK f 0x41—Bits[4-0] CSC B3 MSBs These bits control the multiple of 128 f used for MCLK out. The default value for the 13-bit B3 is 0x1E89. Table 19. MCLK f _N [2:0] Multiple 0x42—Bits[7:0] CSC B3 LSBs...
Page 32 AD9381 0x5E—Bits[7:6] Channel Status Mode 0x81—Bits[1:0] Scan Information Table 24. 0x5E—Bits[5:3] PCM Audio Data S [1:0] Scan Type 0x5E—Bit[2] Copyright Information No information 0x5E—Bit[1] Linear PCM Identification Overscanned (television) 0x5E—Bit[0] Use of Channel Status Block Underscanned (computer) 0x5F—Bits[7:0] Channel Status Category Code 0x60—Bits[7:4] Channel Number...
Page 33 AD9381 0x87—Bits[6:0] New Data Flags (NDF) 0x91—Bits[7:4] Audio Coding Type This register indicates whether data in specific sections has These bits identify the audio coding so that the receiver may changed. In the address space from 0x80 to 0xFF, each register process audio properly.
Page 34 AD9381 Table 33. Channel Number Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 – – – – – – – – –...
Page 35 AD9381 0xA3—Bits[7:0] PD2 0xBD—Bit[4] Field Repeat 0xA4—Bits[7:0] PD3 This defines whether the field is new or repeated. 0 = new field 0xA5—Bits[7:0] PD4 or picture. 1 = repeated field. 0xA6—Bits[7:0] PD5 0xBD—Bits[1:0] MPEG Frame 0xA7—Bits[6:0] New Data Flags This identifies the frame as I, B, or P.
Page 36 AD9381 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xDD—Bits[7:0] ISRC2_PB1 0xCA—Bits[7:0] ISRC1_PB1 0xDE—Bits[7:0] ISRC2_PB2 0xCB—Bits[7:0] ISRC1_PB2 0xDF—Bits[6-0] New Data Flags 0xCC—Bits[7:0] ISRC1_PB3 See Register 0x87 for a description. 0xCD—Bits[7:0] ISRC1_PB4 0xE0—Bits[7:0] ISRC2_PB3 0xCE—Bits[7:0] ISRC1_PB5 0xE1—Bits[7:0] ISRC2_PB4 0xCF—Bits[6:0] New Data Flags 0xE2—Bits[7:0] ISRC2_PB5 See Register 0x87 for a description.
Page 37: 2-Wire Serial Control Port
SCL and SDA are pulled high by external pull-up resistors. To write data to specific control registers of the AD9381, the 8- Data received or transmitted on the SDA line must be stable for bit address of the control register of interest must be written the duration of the positive-going SCL pulse.
Page 38: Serial Interface Read/Write Examples
AD9381 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: Read from one control register: • • Start signal Start signal • • Slave address byte (R/ W bit = low) Slave address byte (R/ W bit = low) •...
Page 39: Pcb Layout Recommendations
The following is a guide for AD9381. The location of the split should be at the receiver of designing a board using the AD9381.
Page 40: Color Space Converter (Csc) Common Settings
AD9381 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 38. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9381) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff 3 Red/Cr Offset Address 0x35 0x36 0x37 0x38...
Page 41 AD9381 Table 42. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Red/Cr Coeff 2 Red/Cr Coeff 3 Red/Cr Offset Address 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C Value 0x08 0x2D 0x18 0x93 0x1F...
Page 42: Outline Dimensions
AD9381 OUTLINE DIMENSIONS 16.00 1.60 MAX BSC SQ 0.75 0.60 0.45 PIN 1 14.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° SEATING 0.08 MAX 0.05 PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 VIEW A 0.17...
Page 43 AD9381 NOTES Rev. 0 | Page 43 of 44...