Analog Devices AD9380 Manual page 27

Hex Read/Write
Address or Read-Only
0x26 Read/Write
0x27 Read/Write
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0x28 Read/Write
0x29 Read/Write
0x2A Read/Write
0x2B Read/Write
0x2C Read/Write
0x2D Read/Write
0x2E Read/Write
Default
Bits Value Register Name
[1] ******1* Primary Output
Enable
[0] *******0
Secondary Output
Enable
[7] 0******* Output Three-State
[6] *0****** SOG Three-State
[5] **0***** SPDIF Three-State
2
[4] ***0**** I S Three-State
[3] ****1*** Power-Down Pin
Polarity
[2:1] *****00*
Power-Down Pin
Function
[0] *******0 Power-Down
[7] 1******* Auto Power-Down
Enable
[6] *0****** HDCP A0
[5] **0***** MCLK External
Enable
[4] ***0**** BT656 EN
[3] ****0*** Force DE Generation
[2:0] *****000 Interlace Offset
[7:2] 011000** VS Delay
[1:0] ******01 HS Delay MSB
[7:0] 00000100 HS Delay
[3:0] ****0101 Line Width MSB
[7:0] 00000000 Line Width
[3:0] ****0010 Screen Height MSB
[7:0] 11010000 Screen Height
[7] 0******* Ctrl EN
2
[6:5] *00***** I S Out Mode
2
[4:0] ***11000 I S Bit Width
Description
Enables primary output.
Enables secondary output (DDR 4:2:2 in Output Modes 1 and 2).
Three-state the outputs.
Three-state the SOG output.
Three-state the SPDIF output.
Three-state the I
Sets polarity of power-down pin.
0 = active low.
1 = active high.
Selects the function of the power-down pin.
00 = power-down.
01 = power-down and three-state SOG.
10 = three-state outputs only.
11 = three-state outputs and SOG.
0 = normal.
1 = power-down.
0 = disable auto-low power state.
1 = enable auto-low power state.
Sets the LSB of the address of the HDCP I
second receiver in a dual-link configuration.
0 = use internally generated MCLK.
1 = use external MCLK input.
If an external MCLK is used, then it must be locked to the video
clock according to the CTS and N available in the I
match between the internal MCLK and the input MCLK results in
dropped or repeated audio samples.
Enables EAV/SAV codes to be inserted into the video output
data.
Allows use of the internal DE generator in DVI mode.
Sets the difference (in HSYNCs) in field length between Field 0
and Field 1.
Sets the delay (in lines) from the VSYNC leading edge to the start
of active video.
MSB, Register 0x29.
Sets the delay (in pixels) from the HSYNC leading edge to the
start of active video.
MSB, Register 0x2B.
Sets the width of the active video line in pixels.
MSB, Register 0x2D.
Sets the height of the active screen in lines.
Allows Ctrl [3:0] to be output on the I
2
00 = I S mode.
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
Sets the desired bit width for right-justified mode.
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2
S output and the MCLK out.
2
C. Set to 1 only for a
2
S data pins.
AD9380
2
C. Any mis-