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Analog Devices AD9380 Manual page 28

Analog/hdmi dual-display interface

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AD9380
Hex
Read/Write
Address
or Read-Only
0x2F
Read
0x30
Read
0x31
Read/Write
0x32
Read/Write
0x33
Read/Write
0x34
Read/Write
0x35
Read/Write
0x36
Read/Write
0x37
Read/Write
0x38
Read/Write
Default
Bits
Value
Register Name
[6]
*0******
TMDS Sync Detect
[5]
**0*****
TMDS Active
[4]
***0****
AV Mute
[3]
****0***
HDCP Keys Read
[2:0]
*****000
HDMI Quality
[6]
*0******
HDMI Content
Encrypted
[5]
**0*****
DVI HSYNC Polarity
[4]
***0****
DVI VSYNC Polarity
[3:0]
****0000
HDMI Pixel
Repetition
[7:4]
1001****
MV Pulse Max
[3:0]
****0110
MV Pulse Min
[7]
0*******
MV Oversample En
[6]
*0******
MV Pal En
[5:0]
**001101
MV Line Count Start
[7]
1*******
MV Detect Mode
www.BDTIC.com/ADI
[6]
*0******
MV Settings Override
[5:0]
**010101
MV Line Count End
[7:6]
10******
MV Pulse Limit Set
[5]
**0*****
Low Freq Mode
[4]
***0****
Low Freq Override
[3]
****0***
Up Conversion Mode
[2]
*****0**
CrCb Filter Enable
[1]
******0*
CSC_Enable
[6:5]
*01* ****
CSC_Mode
[4:0]
***01100
CSC_Coeff_A1 MSB
[7:0]
01010010
CSC_Coeff_A1 LSB
[4:0]
***01000
CSC_Coeff_A2 MSB
[7:0]
00000000
CSC_Coeff_A2 LSB
Description
Detects a TMDS DE.
Detects a TMDS clock.
Gives the status of AV mute based on general control packets.
Returns 1 when read of EEPROM keys is successful.
Returns quality number based on DE edges.
This bit is high when HDCP decryption is in use (content is
protected). The signal goes low when HDCP is not being used.
Customers can use this bit to determine whether or not to allow
copying of the content. The bit should be sampled at regular
intervals because it can change on a frame by frame basis.
Returns DVI HSYNC polarity.
Returns DVI VSYNC polarity.
Returns current HDMI pixel repetition amount. 0 = 1×, 1 = 2×, ...
The clock and data outputs automatically decimate by this value
to present the data in the original form.
Sets the maximum pseudo sync pulse width for Macrovision
detection.
Sets the minimum pseudo sync pulse width for Macrovision
detection.
Tells the Macrovision detection engine whether we are
oversampling or not.
Tells the Macrovision detection engine to enter PAL mode.
Sets the start line for Macrovision detection.
0 = standard definition.
1 = progressive scan mode.
0 = use hard-coded settings for line counts and pulse widths.
2
1 = use I
C values for these settings.
Sets the end line for Macrovision detection.
Sets the number of pulses required in the last 3 lines (SD mode
only).
Sets audio PLL to low frequency mode. Low frequency mode
should only be set for pixel clocks <80 MHz.
Allows the previous bit to be used to set low frequency mode
rather than the internal auto-detect.
0 = repeat Cr and Cb values.
1 = interpolate Cr and Cb values.
Enables the FIR filter for 4:2:2 CrCb output.
Enables the CSC. The default settings for the CSC provide HDTV-
to-RGB conversion.
Sets the fixed point position of the CSC coefficients, including
the A4, B4, and C4 offsets.
00 = ±1.0, −4096 to +4095.
01 = ±2.0, −8192 to +8190.
1× = ±4.0, −16384 to +16380.
MSB, Register 0x36.
Color space converter (CSC) coefficient for equation:
R
= (A1 × R
OUT
IN
G
= (B1 × R
OUT
IN
B
= (C1 × R
OUT
IN
B
MSB, Register 0x38.
CSC coefficient for equation:
R
= (A1 × R
OUT
IN
G
= (B1 × R
OUT
IN
B
= (C1 × R
OUT
IN
B
Rev. 0 | Page 28 of 60
) + (A2 × G
) + (A3 × B
) + A4
IN
IN
) + (B2 × G
) + (B3 × B
) + B4
IN
IN
) + (C2 × G
) + (C3 × B
) + C4
IN
IN
+ (A2 × G
) + (A3 × B
) + A4
IN
IN
) + (B2 × G
) + (B3 × B
) + B4
IN
IN
) + (C2 × G
) + (C3 × B
) + C4
IN
IN

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