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ADLINK Technology NuDAQ PCIe-9100 Series User Manual

Multiplexer/simultaneous multifunction data acquisition card
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NuDAQ
Multiplexer/Simultaneous
Multifunction Data Acquisition Card
Manual Revision: 1.2
Revision Date:
Part No:
PCIe-9100 Series
User's Manual
May 5, 2024
50M-18904-1020

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Summary of Contents for ADLINK Technology NuDAQ PCIe-9100 Series

  • Page 1 ® NuDAQ PCIe-9100 Series Multiplexer/Simultaneous Multifunction Data Acquisition Card User’s Manual Manual Revision: 1.2 Revision Date: May 5, 2024 Part No: 50M-18904-1020...
  • Page 2 Revision History Revision Release Date Description of Change(s) 2023-02-21 Initial release Update product name to PCIe-9100 Series. 2023-06-01 Add PCIe-9103. 2024-05-05 Add PCIe-9146 and PCIe-9147.
  • Page 3 PCIe-9100 Series Preface Copyright © 2024 ADLINK Technology, Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. Additional information, aids, and tips that help users perform tasks. NOTE: NOTE: Information to prevent minor physical injury, component dam- age, data loss, and/or program corruption when trying to com- plete a task.
  • Page 5 PCIe-9100 Series Table of Contents Revision History..............ii Preface ..................iii 1 Introduction ................ 1 Functions ................1 Features................1 Applications ................. 3 Specifications............... 4 Software Support ............... 12 2 Getting Started ..............15 Package Contents ............. 16 Device Layout and I/O Connectors........17 Switch and Jumper Settings ..........
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  • Page 7 PCIe-9100 Series Introduction The PCIe-9100 Series of products are PCI Express multifunction data acquisition cards for industrial applications. The plug and play feature of the PCI Express bus architecture makes it easy for users to quickly install PCIe-9100 Series products on their sys- tems.
  • Page 8 D/A conversion  Up to 2 channels D/A output with waveform generation  capability Up to 1MHz D/A sampling rates  1K samples output data FIFO for DA channels  D/A Data transfer: software update and bus-mastering  DMA with Scatter/Gather functionality 2 trigger modes: Post trigger, Post trigger with re-trigger ...
  • Page 9 PCIe-9100 Series 1.3 Applications  Cable Testing  Laboratory Automation  Industrial process control and monitoring  Vibration and transient analysis  Power monitoring  Biotech measurement  Medical instrumentation  Introduction...
  • Page 10 1.4 Specifications 1.4.1 General Specifications Model PCIe-9101/9121/9141 PCIe-9103 PCIe-9146/9147 Analog Input Simultaneous/Scanning Scanning Scanning Simultaneous PCIe-9146: 4-ch 16 single-ended (SE) or 32 single-ended (SE) or Number of Channels PCIe-9147: 8-ch 8 differential input (DI) 16 differential input (DI) differential input (DI) PCIe-9101: 250 kS/s Single- PCIe-9121: 800 kS/s...
  • Page 11 PCIe-9100 Series Model PCIe-9101/9121/9141 PCIe-9103 PCIe-9146/9147 Integral Nonlinearity (INL) <1 LSB Differential Nonlinearity (DNL) <1 LSB CMRR @ 60 Hz 85 dB Analog Output (AO) Number of Channels Max. Updating Rate 1MS/s 1MS/s Resolution 16-bit 16-bit Output Range ±10 V ±10 V 1K samples 1K samples...
  • Page 12 Model PCIe-9101/9121/9141 PCIe-9103 PCIe-9146/9147 General Purpose Digital IO (DIO) Digital Input: 16 channels Number of Channels Digital Output: 16 channels Digital Type Isolation 2500Vrms Digital Input: Low Digital Input: Low Digital Input: Low Power-on Status Digital Output: Low Digital Output: Open Digital Output: Low 512 samples for all DI 512 samples for all DI...
  • Page 13 PCIe-9100 Series Model PCIe-9101/9121/9141 PCIe-9103 PCIe-9146/9147 Software trigger, Software trigger, Software trigger, External digital trigger Trigger Source External digital trigger External digital trigger (CN1 Pin 53 for DI, CN1 (CN3.17) (CN4.8) Pin 54 for DO) Post trigger Trigger Modes Post trigger with re-trigger Programmed I/O, Programmed I/O, Data Transfers...
  • Page 14 Model PCIe-9101/9121/9141 PCIe-9103 PCIe-9146/9147 Mechanical & Environmental Bus Type PCI Express 1.0 Bus Width x1 Lane Connector 37-pin D-type connector 68-pin SCSI-type female 181.05 (L) x 19.4 (W) x Dimensions (mm) 169.55 (L) X 16.15 (W) X 98.4 (H) 126.72 (H) Weight 118.8 g 100 g...
  • Page 15 PCIe-9100 Series 1.4.2 Performance Specifications 1.4.2.1 Large Signal Bandwidth Large Signal Bandwidth (-3db with 0.9 of FSR of Input) Input Range ±10V ±5V ±2.5V ±1.25V ±0.625V ±0.3125V PCIe-9101 330kHz 400kHz 470kHz 470kHz 460kHz 470kHz PCIe-9103 420kHz 720kHz 730kHz 720kHz 730kHz 730kHz PCIe-9121 380kHz...
  • Page 16 1.4.2.3 System Noise System noise (LSBrms) Input Range ±10V ±5V ±2.5V ±1.25V ±0.625V ±0.3125V PCIe-9101 PCIe-9103 PCIe-9121 PCIe-9141 PCIe-9146 PCIe-9147 Table 1-4: System Noise 1.4.2.4 CrossTalk CrossTalk (dB) Input Range ±10V ±5V ±2.5V ±1.25V ±0.625V ±0.3125V PCIe-9101 PCIe-9103 PCIe-9121 PCIe-9141 PCIe-9146 -100 PCIe-9147...
  • Page 17 PCIe-9100 Series 1.4.2.6 Drift – Gain Drift – Gain (LSB per C) Input Range ±10V ±5V ±2.5V ±1.25V ±0.625V ±0.3125V PCIe-9101 PCIe-9103 PCIe-9121 PCIe-9141 PCIe-9146 PCIe-9147 Table 1-7: Drift – Gain 1.4.2.7 Settling Time to Full-scale Step for ±2 LSB Settling time to full-scale step for ±2 LSB (μs) Input Range ±10V ±5V ±2.5V ±1.25V ±0.625V ±0.3125V...
  • Page 18 1.5 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from pro- gramming libraries, such as DLLs, for most Windows-based sys- tems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website.
  • Page 19 PCIe-9100 Series 1.5.1 MAPS Core ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access.
  • Page 20 1.5.2 MAPS/LV, LabVIEW Support Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample pro- gram for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual: https://www.adlinktech.com/Products/Data_Acquisition/...
  • Page 21 PCIe-9100 Series Getting Started This chapter describes the proper installation environment, installation procedures, package contents and basic information users should be aware of. Diagrams and images of equipment illustrated are for refer- ence only. Actual system configuration and specifications may vary.
  • Page 22 2.1 Package Contents Before continuing, check the package contents for any damage and check if the following items are included in the packaging: PCIe-9100 Series Multi-Function Data Acquisition Card  Product Warranty Card  The card contains electro-static sensitive components that can easily be damaged by static electricity.
  • Page 23 PCIe-9100 Series 2.2 Device Layout and I/O Connectors 2.2.1 PCIe-9101 PCB Layout Figure 2-1: PCIe-9101 PCB Front Layout Getting Started...
  • Page 24 Figure 2-2: PCIe-9101 PCB Rear Layout Getting Started...
  • Page 25 PCIe-9100 Series 2.2.2 PCIe-9103 PCB Layout Figure 2-3: PCIe-9103 PCB Layout Getting Started...
  • Page 26 2.2.3 PCIe-9121/9141 PCB Layout Figure 2-4: PCIe-9121/9141 PCB Layout Getting Started...
  • Page 27 PCIe-9100 Series 2.2.4 PCIe-9146/9147 PCB Layout PP &1 '2 %XIIHU /LQH 'ULYHU ', %XIIHU '$& &1 )3*$ PP $'& 3&,H %ULGJH Figure 2-5: PCIe-9146/9147 PCB Layout Getting Started...
  • Page 28 2.3 Switch and Jumper Settings The following item can be configured with jumpers: analog output range on PCIe-9101  5V or 12V output setting on CN1 Pins 15, 49 on PCIe-9146/  9147 The card's jumpers and switches are preset at the factory. You can change the jumper settings for your own applications.
  • Page 29 PCIe-9100 Series 2.3.1 D/A Reference Voltage Settings The D/A converter's reference voltage source can be supplied both internally and externally. The external reference voltage comes from connector CN3, Pin 31 (ExtRef1) and Pin12 (ExtRef2). The reference source of the D/A channel 1 and channel 2 are selected by JP4.
  • Page 30 E W E W E W Figure 2-6: PCIe-9146/9147 CN8 Settings Definition Pin No, Definition +12V or 5V +12V or 5V Table 2-3: PCIe-9146/9147 5V/12V Output Pin on CN1 Pin Assignments Getting Started...
  • Page 31 PCIe-9100 Series 2.3.2 Board ID (SW1) The PCIe-9100 Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are multiple cards on the same platform, this board ID switch is useful for iden- tifying each card’s device number.
  • Page 32 2.4 Connector Pin Assignments 2.4.1 PCIe-9101/9121/9141/9103 The PCIe-9101/9121/9141/9103 comes equipped with two 20-pin insulation displacement connectors (CN1 and CN2) and one 37- pin D-type connector (CN3). CN1 and CN2 are located on the board and CN3 is located on the faceplate. CN1 is for digital signal input, CN2 is for digital signal output, and CN3 is for analog input/output and timer/counter signals.
  • Page 33 PCIe-9100 Series (For single-ended connection) (For differential connection) AIH0 AI16 AIL0 AIH1 AI17 AIL1 AIH2 AI18 AIL2 AIH3 AI19 AIL3 AIH4 AI20 AIL4 AIH5 AI21 AIL5 AIH6 AI22 AIL6 AIH7 AI23 AIL7 A.GND A.GND A.GND A.GND AIH8 AIL8 AI24 AIH9 AIL9 AI25 AIH10...
  • Page 34 Signal Name Description AI <0…31> Signal-ended Analog Input Channels 0-31 AIH <0…15> Differential Analog High Input Channels 0-15 AIL <0…15> Differential Analog Low Input Channels 0-15 ExtRef <1,2> External Reference Voltage for D/A CH <1,2> AO <0,1> Analog Output Channels <0,1> ExtCLK External Clock ExtTrig...
  • Page 35 PCIe-9100 Series DO 0 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7 DO 8 9 10 DO 9 DO 10 11 12 DO 11 DO 12 13 14 DO 13 DO 14 15 16 DO 15 17 18 19 20...
  • Page 36 Signal Name Description DI <0…15> Digital Input signal channels 0-15 DO <0…15> Digital Output signal channels 0-15 DI_SYNC_IN Digital Input synchronization clock source in DO_SYNC_OUT Digital Output synchronization clock source out Digital Ground +12V 12V power output @ 0.2A 5V power output @ 0.2A EICOM<1...4>...
  • Page 37 PCIe-9100 Series Signal Name Description COUT Output of Counter ExtTrg In External A/D Trigger Signal +5V output Ground Table 2-7: CN4 Pin Assignment Legend 2.4.2 PCIe-9146/9147 The PCIe-9146/9147 comes equipped with one 68-pin SCSI-type female connector (CN1). CN1 is located on the faceplate which is used for analog input/output, digital signal input/output, timer/ counter signals and encoder signals.
  • Page 38 AI_AO_Cal+ AI_AO_Cal- AGND AGND AIH3 AIL3 AGND AGND AIH2 AIL2 AIH1 AIL1 AGND AGND AIH0 AIL0 AGND AGND +12V or 5V +12V or 5V Ext. Time Base or GPTC CLK0 Ext. CONVSN. or GPTC CLK1 DI0 / DI0 / EA0+ DI8 / GPTC GATE0 / EA0- DI1 / DI1 / EB0+ DI9 / GPTC GATE1 / EB0-...
  • Page 39 PCIe-9100 Series AIH7 AIL7 AI_AO_Cal+ AI_AO_Cal- AIH6 AIL6 AIH5 AIL5 AGND AGND AIH4 AIL4 AIH3 AIL3 AGND AGND AIH2 AIL2 AIH1 AIL1 AGND AGND AIH0 AIL0 AGND AGND +12V or 5V +12V or 5V Ext. Time Base or GPTC CLK0 Ext.
  • Page 40 Signal Name Description AIH <0…7> Differential Analog High Input Channels 0-7 AIL <0…7> Differential Analog Low Input Channels 0-7 AO <0,1> Analog Output Channels <0,1> AGND Analog Ground Ext. Time Base External Time Base Clock Signal Input Ext. CONVSN External Conversion Clock Signal Input AI Trigger In External Analog Input Trigger Signal Input AO Trigger In...
  • Page 41 PCIe-9100 Series 2.5 Hardware Installation Outline 2.5.1 PCI Express Configuration PCI Express cards are equipped with a plug and play PCI Express controller that can request base addresses and interrupts accord- ing to the PCI Express standard. The system BIOS will configure resources based on the PCI Express cards’...
  • Page 42 2.6 Device Installation for Windows Systems Once Windows 7/10/11 or later has started, the Plug and Play function of Windows system will find the new NuDAQ cards. If this is the first time the NuDAQ cards are running on your Windows system, you will be prompted to input the device information source.
  • Page 43 PCIe-9100 Series Operation Theory This chapter describes the operation theory of the PCIe-9100 Series card functions. The functions include A/D conversion, D/A conversion, Digital I/O and counter/timer usage. The operation theory can help you to understand how to configure or to program the PCIe-9100 Series cards.
  • Page 44 3.2 Analog Input Signal Connection The PCIe-9100 Series provides single-ended or differential analog input channels. The analog signals can be converted to digital values by the A/D converter. To avoid ground loops and to obtain more accurate measurements, it is important to understand the signal source type and how to choose the ana- log input modes, either signal-ended or differential.
  • Page 45 PCIe-9100 Series Differential Input Mode The differential input mode provides two inputs that respond to differences in signals. If the signal source has one side con- nected to local ground, the differential mode can be used to reduce the effect of ground loops. Figure 3-2 shows the con- nection for differential input mode.
  • Page 46 A differential mode must be used when the signal source is dif- ferential. A differential source means that the ends of the signal are not grounded. To avoid the danger of high voltages between the local ground of the signal and the ground of the PC system, a shorted ground path must be connected.
  • Page 47 PCIe-9100 Series 3.2.1 A/D Conversion Procedure A/D conversion starts when a trigger is set by the trigger source. The PCIe-9100 Series provides three trigger modes. See section 3.2.2. The A/D data should now be transferred into the PC's memory for further processing. The PCIe-9100 Series provides three data transfer modes that allow users to optimize the DAQ sys- tem.
  • Page 48 External Digital Trigger Through Pin ExtTrig, an external digital trigger is generated when a TTL rising edge or falling edge is detected. The trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 50 ns.
  • Page 49 PCIe-9100 Series Above-High analog trigger condition Figure 3-6 shows the above-high analog trigger condition. The trigger signal is generated when the input analog signal is higher than the High_Threshold voltage. The Low_Threshold setting is not used in this trigger condition. Figure 3-6: Above-High analog trigger condition Inside-Region analog trigger condition Figure 3-7 shows the inside-region analog trigger condition.
  • Page 50 High-Hysteresis analog trigger condition Figure 3-8 shows the high-hysteresis analog trigger condition. The input analog signal level should greater than Low_Threshold voltage at first, and then the trigger signal will be generated when the input analog signal level is greater than High_Threshold voltage to determine the hysteresis duration.
  • Page 51 PCIe-9100 Series Low-Hysteresis analog trigger condition Figure 3-9 shows the low-hysteresis analog trigger condition. The input analog signal level should be lower than the High_Threshold voltage at first, and then the trigger signal will be generated when the input analog signal level is lower than Low_Threshold voltage to determine the hysteresis duration.
  • Page 52 3.2.3 A/D Trigger Modes There are 4 trigger modes (pre-trigger, post-trigger, middle-trig- ger, delay-trigger, post-trigger with re-trigger and delay-trigger with re-trigger) working with the 3 trigger sources to initiate dif- ferent scan data acquisition timing when a trigger event occurs. Pre-Trigger Acquisition Use pre-trigger acquisition in applications where you want to collect data before a trigger event.
  • Page 53 PCIe-9100 Series If a trigger event occurs when a scan is in progress, the data acquisition will not stop until the scan completes, and the stored M scans of data includes the last scan. Therefore, the first stored data will always be the first channel entry of a scan (that is, the first channel entry in the Channel Gain Queue if the number of entries in the Channel Gain Queue is equivalent to the value of NumChan_counter), no matter when a trigger sig-...
  • Page 54 Figure 3-12: Pre-trigger with M_enable=0 (Trigger occurs before M scans) [Max. value of M_counter is 65536] Figure 3-13: Pre-trigger with M_enable=1 Operation Theory...
  • Page 55 PCIe-9100 Series Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter.
  • Page 56 If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 3-15. Figure 3-15: Middle trigger (trigger occurs when a scan is in progress) M_counter defined in Middle-Trigger is different from that of Pre-Trigger.
  • Page 57 PCIe-9100 Series Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC_counter, as illustrated in Figure 3- 16. The total acquired data length = number of enable-channel * PSC_counter.
  • Page 58 Delay-Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trig- ger event. The delay time/samples are controlled by the value, which is pre-loaded in the Delay_counter (16-bit). The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met.
  • Page 59 PCIe-9100 Series Post-Trigger or Delay-Trigger Acquisition with Re-trigger Use post-trigger or delay-trigger acquisition with the re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC_counter, and users can program Retrig_no to specify the number of re-triggers.
  • Page 60 3.2.4 A/D Data Transfer Modes Any of the two A/D data transfer modes can be used when a conversion is completed. The Data Transfer Mode is controlled by the A/D mode control bits of the A/D control register. The dif- ferent transfer modes are specified below.
  • Page 61 PCIe-9100 Series 3.2.5 AI Data Format The data format of the acquired 16- and 14-bit A/D data is 2’s complement coding. Table 3-1 and Table 3-2 show the valid input ranges and the ideal transfer characteristics. Digital Description Bipolar Analog Input Range Code (16-bit) Full-scale...
  • Page 62 3.3 D/A Conversion For complex applications, the PCIe-9100 Series offer software polling to update the output, and DMA data transfer to generate waveforms. This means that the D/A update rate is not only controlled by software timing, but can also be set by a precision hardware timer that is user specified.
  • Page 63 PCIe-9100 Series Definition Pin No, Definition AGND AGND Ext. Time Base AO Trigger In DGND Table 3-4: PCIe-9146/9147 Analog Output Mode on CN1 Pin Assignments 3.3.1 Bipolar Output Modes The PCIe-9100 Series series supports a maximum ±10 V volt- age output. Table 3-5 illustrates the relationship of straight binary coding between the digital codes and output voltages.
  • Page 64 3.3.2 Software Update This method is suitable for applications that need to generate D/A output controlled by user programs. In this mode, the D/A converter generates one output once the software command is issued. However, it is difficult to determine the software update rate under a multitasking OS such as Windows.
  • Page 65 PCIe-9100 Series Waveform Generation Clock Source When the onboard DAC receives a conversion clock signal, it will trigger a D/A update. The update clock of PCIe-9100 Series may come from two different clock sources: internal hardware timer, or external timebase clock source (CN3 pin 37). You can choose the update clock source by setting the AO source con- figuration Waveform Generation with Internal Hardware Timer...
  • Page 66 Figure 3-20: Typical D/A Timing of Waveform Generation Operation Theory...
  • Page 67 PCIe-9100 Series 3.3.4 Trigger Modes Post-Trigger Generation Use post-trigger generation when you want to generate a waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC_counter* IC_counter, illustrated in Figure 3-21. Figure 3-21: Post-Trigger Generation Operation Theory...
  • Page 68 Post-Trigger with Retrigger Use post-trigger with retrigger to generate multiple waveforms with respect to multiple incoming trigger signals. Set Trig_counter to specify the number of acceptable trigger sig- nals. Figure 3-22 Iillustrates two waveforms generated after the first trigger signal. The card then waits for another trigger sig- nal.
  • Page 69 PCIe-9100 Series Iterative Waveform Generation You can set the IC_counter to generate iterative waveforms regardless of the trigger mode used. The IC_counter stores the iteration number. Examples are shown in Figure 3-23 and Figure 3-24. When IC_counter is disabled, the waveform generation will not stop until a stop trigger is asserted.
  • Page 70 Figure 3-23: Finite Iterative Waveform Generation with Post-trigger Operation Theory...
  • Page 71 PCIe-9100 Series Figure 3-24: Infinite Iterative Waveform Generation with Post-trigger Operation Theory...
  • Page 72 3.4 Digital Input and Output Definition Pin No, Definition DI10 DI11 DI12 DI13 DI14 DI15 DI_SYNC_IN Table 3-7: PCIe-9101/9121/9141 DIO Mode Pin Assignments on CN1 Definition Pin No, Definition DO10 DO11 DO12 DO13 DO14 DO15 DI_SYNC_OUT Table 3-8: PCIe-9101/9121/9141 DIO Mode Pin Assignments on CN2 Operation Theory...
  • Page 73 PCIe-9100 Series Definition Pin No, Definition DI10 DI11 DI12 DI13 DI14 DI15 DGND DO10 DO11 DO12 DO13 DO14 DO15 DGND Table 3-9: PCIe-9146/9147 Digital Input/Output Mode on CN1 Pin Assignments 3.4.1 TTL Compatible The PCIe-9100 Series provides 16 digital input and 16 digital output channels through the connectors CN1 and CN2 on- board.
  • Page 74 data to the corresponding registers. Note that the DIO data channel can only be read or written to in groups of 16 bits. It is impossible to access individual bits. Digital Input(DI) From TTL Signal Digital Output (DO) To TTL Devices Digital GND (DGND) PCI-91 Series Outside Device...
  • Page 75 PCIe-9100 Series Definition Pin No, Definition DO10 DO11 DO12 DO13 DO14 DO15 EOGND EOGND Vpower Vpower Table 3-11: PCIe-9103 DIO Mode Pin Assignments on CN2 3.4.2.1 Isolated Digital Input There are 16 Isolated Digital input signals. Each digital input signal is connect to a photo isolator such that the signal is iso- lated from the ground or the power plane of the host PC.
  • Page 76 Note that the 16 DI signals are partitioned into 4 groups. Each group is based on a common plane. Every group is mutually isolated. Refer to Figure 3-27 and Table 3-12 for the four groups. Signal Names Common Signal ID_0 to ID_3 EICOM1 ID_4 to ID_7 EICOM2...
  • Page 77 PCIe-9100 Series The following diagram shows the EICOM as common power. An external device or circuit will provide the power source and current sink. Most open collector output devices can be connected to the PCIe-9103 using this configuration. I s o l a t e d I n p u t 2 .
  • Page 78 3.4.2.2 Isolated Digital Output There are 16 Isolated Digital output signals. Darlington transis- tors drive the digital output signals. Figure 3-29 shows the out- put circuits. Note that the 16 DO signals uses a common ground and com- mon external power source. Vpower From digital circuits DO_n...
  • Page 79 PCIe-9100 Series If the load is inductive such as from a relay, the diagram below can be used. The power supply must be from an external source in order to form a fly-wheel current loop. Vpower Power From digital circuits Supply DO_n Load...
  • Page 80 3.5 General Purpose Timer/Counter The PCIe-9100 Series comes with up to four general purpose timer/counter sets featuring: Count up/down controlled by hardware or software  Programmable counter clock source (internal clock up to 33  MHz, external clock up to 8 MHz) Programmable gate selection (hardware or software con- ...
  • Page 81 PCIe-9100 Series Definition Pin No, Definition GPTC CLK0 GPTC CLK1 GPTC GATE0 GPTC GATE1 GPTC COUT0 GPTC COUT1 DGND Table 3-15: PCIe-9146/9147 Digital Input/Output Mode on CN1 Pin Assignments Operation Theory...
  • Page 82 3.5.1 Basic Timer/Counter Functions Each timer/counter has three inputs that can be controlled via hardware or software applications: clock input (GPTC_CLK), gate input (GPTC_GATE), up/down control input (GPTC_UD). The GPTC_CLK input provides a clock source input to the timer/counter controlled by software which can switch the clock source internally or externally.
  • Page 83 PCIe-9100 Series Mode 1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC_CLK after software-start. Initial count can be loaded from software. The current count value can be read back by software any time with no effect on the counting. GPTC_GATE is used to enable/disable counting.
  • Page 84 Mode 2: Single Period Measurement The counter counts the period of the signal on GPTC_GATE in terms of GPTC_CLK. The initial count can be loaded from soft- ware. After software-start, the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE.
  • Page 85 PCIe-9100 Series Mode 3: Single Pulse-width Measurement The counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. The initial count can be loaded from software. After software-start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is in its active state.
  • Page 86 Mode 4: Single Gated Pulse Generation This generates a single pulse with programmable delay and programmable pulse-width following software-start. The two programmable parameters can be specified in terms of periods of the GPTC_CLK input by software. GPTC_GATE is used to enable/disable counting.
  • Page 87 PCIe-9100 Series Mode 5: Single Triggered Pulse Generation This mode generates a single pulse with programmable delay programmable pulse-width following active GPTC_GATE edge. You may specify these programmable parameters in terms of periods of the GPTC_CLK input. When the first GPTC_GATE edge triggers the single pulse, GPTC_GATE takes no effect until software-start is executed again.
  • Page 88 Mode 6: Re-triggered Single Pulse Generation This mode is similar to Mode 5 except that the counter gener- ates a pulse following every active edge of GPTC_GATE. After software-start, every active GPTC_GATE edge triggers a sin- gle pulse with programmable delay and pulsewidth. Any GPTC_GATE triggers that occur when the prior pulse is not completed is ignored.
  • Page 89 PCIe-9100 Series Mode 7: Single Triggered Continuous Pulse Generation This mode is similar to Mode 5 except that the counter gener- ates continuous periodic pulses with programmable pulse inter- val and pulse-width following the first active edge of GPTC_GATE. When the first GPTC_GATE edge triggers the counter, GPTC_GATE takes no effect until software-start is executed again.
  • Page 90 3.5.3 PWM Modes The PCIe-9100 Series powerful timer/counter can also simu- late a PWM (Pulse Width Modulation) output. By setting vary- ing number of Pulse_initial_cnt and Pulse_length_cnt, you can get a varying pulse frequency (Fpwm) and duty cycle (Dutypwm). This parameters can change immediately when PWM mode is operating COF (Change on the Fly).
  • Page 91 PCIe-9100 Series 3.6 Encoder The PCIe-9100 Series features a simple motion control with support for two channel encoder input sets which provide an alternative for a step motor or servo motor's position feedback. The encoder sets are assigned in CN1. Definition Pin No.
  • Page 92 Encoder Input Module Figure 3-41 illustrates the encoder isolation phase A, phase B and phase Z inputs module. Figure 3-41: Encoder Input Module The Encoder OGRx input is different from the encoder phase input since you need to add external +24V power to drive the photo- couple.
  • Page 93 PCIe-9100 Series CW/CCW Encoder Mode When the Encoder is set to CW/CCW mode and when the input EAx is connected to a CW source signal and EBx is connected to a CCW source signal, pulses from EAx will cause the counter to count up and spin the motor clockwise.
  • Page 94 X1 Encoder Mode In X1 encoder mode, if phase A (EA0/EA1) is ahead of phase B (EB0/EB1) in a quadrature cycle, the counter value will increase by 1. Otherwise, if phase B is ahead of phase A in a quadrature cycle, the counter value will decrease by1.
  • Page 95 PCIe-9100 Series X4 Encoder Mode This mode is similar to X1 Encoder Mode, except that the amount of the counter value increases or decreases by four. Refer to Figure 3-46. Figure 3-46: X4 Encoder Mode Operation Theory...
  • Page 96 Phase Z Each encoder mode can use a third phase, phase Z, that is also frequently used for the index phase. You can decide if the counter needs to reload a specified value when phase Z is at a logic high level with phase A and B at a specific logic condition.
  • Page 97 PCIe-9100 Series Original Signal (ORGx) Original Signal (ORG0/ORG2/ORG1) is used with phase Z. With ORG enabled, a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle. When you use the ORG signal if it is at a low level and phase Z is at a high level, then the counter reload is ignored.
  • Page 98 3.7 Programmable Function I/O The PCIe-9146/9147 supports a powerful programmable func- tion I/O provided by an FPGA chip. These functional I/Os can be configured to three modes by software. Mode 0: TTL compatible Digital Input/Output (See “Digital  Input and Output” on page 66.) Mode 1: 32-bit timer/counters (See “General Purpose ...
  • Page 99 PCIe-9100 Series Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.
  • Page 100 Never attempt to repair the device, which should only be  serviced by qualified technical personnel using suitable tools A Lithium-type battery may be provided for uninterrupted  backup or emergency power. Risk of explosion if battery is replaced with one of an incorrect type;...
  • Page 101 PCIe-9100 Series BURN HAZARD Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching. RISQUE DE BRÛLURES Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher.
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  • Page 103 San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com ADLINK Technology GmbH Hans-Thoma-Straße 11...

This manual is also suitable for:

Nudaq pcie-9101Nudaq pcie-9121Nudaq pcie-9141Nudaq pcie-9103Nudaq pcie-9146Nudaq pcie-9147