Mode; Uart Registers; Mode Registers La And 2A Format - Digital Equipment VAXstation I Service Manual

PROGRAMMING INFORMATION
Table 2·11: IMR Bits (continued)
+ - - • - - - . + - - • -
~
. - - - - - - - . - • - - • . - • . - • - • - - • - • - - . • . • - . - • • • - - - • • . • • • . • +
I
BITS
I
DESCRIPTION
I
+·. - - •. ·+· .• - . - - - - - - - - - .. - • - • - • - - • - .•..••.•.• - ..• - • - ..••.••. - - - ·+
02 IM -- Interrupt Mode. When set, polled mode is
selected, and group interrupt disabled. The controller
will not interrupt the CPU. To respond determine if
there are any pending interrupts, the CPU must read the
ICSR. When cleared, interrupt mode is selected, and
group interrupt functions normally.
01 vs -- vector Selection. When cleared, each interrupt
will generate its own vector (contained in Response
Memory). When set, all interrupts generate the same
vector (request level
0
vector).
00 PM·- Priority Mode. When cleared (fixed priority),
level 0 interrupt requests are the highest priority,
level 7 the lowest. When set (rotating priority), the
last interrupt level serviced becomes the lowest
priority level.
+·. - - - • -+· •.... - . - - . - - - .... - - .•.•. - ...•..•....•...... - ........• -+
2.1.6 UART Registers
2.1.6.l Mode Registers lA And 2A · These UART registers are
accessed
by
two successive references to the same I/0 address.
lA:
15 08 07 06 05 04 03 02 01 00
+·. - - . - . - . - - . - - - . - - .. - - • - - - - - - . -+· - -+·. -+· - ·+· ... - . ·+-. ·+-. - ..• ·+
not used RRC:RIS ERM, PAR MOD:PAT,8/CHAR
+- - - - - . - .... - - - - - .. - •. - - •. - . - - - ·+- - ·+- - ·+- - ·+· .... - -+· - -+-. - - . - ·+
.
2A:
15
08 07 06 05 04 03 00
+-. - - . - - - - - . - - . - - . - - - - - - .. - . - - -
·+· ... - .
·+·. -+- - ·+· - - . - - - - . - - - - - ·+
not used :CH MODE1TRC'CET!STOP BIT LENGTH
+- .. - - - - - - - - •. - •. - - - - • - • - • - • - - -
-+- - - - - . -+-. -+-. -+- - - - - - - - - - - •• -
-+
ADDRESS
=
CSR
BASE
+
32
Figure 2·8: Mode Registers lA and 2A Format
2-12