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PROGRAMMING IRFORJIATIOR
Table 2·16:
Interrupt Status/Mask Register Bits
+- - - - - - - -+- - - - ... ·+· •••••... - - •. - - - .....• - . - . - . - . - - ••.•...•.. - .. +
!
BITS
I
ACCESS
I
DESCRIPTION
I
+-. - - . - .
·+· - . - .. -
-+~
... - . - ..... - . - - - ... - .... - ...... - .... - . - .... ·+
<15:08>
(not used)
<07>
READ
<06>
READ
<05>
READ
<04>
READ
<03>
READ
<02>
READ
<01>
READ
<00>
READ
<07:00>
WRITE
Input port change (l •yes).
Change in break B (l •yes).
Receiver ready/FIFO full B (l •yes).
Transmitter ready B (l =yes).
Counter ready (l •yes).
Change in break
A (1
•yes).
Receiver ready/FIFO full A (l •yes).
Transmitter ready
A
(l •yes).
Bit-for-bit mask to enable interrupt
request
asscociated
with
the
above
status
bits
(00000010
=
enable Receiver
Ready
interrupt
on channel A).
~
+········+········+·············································+
2-17
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