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PROGRAMMING INFORMATION
2.1.s.s
ISR · The 8-bit Interrupt Service .Register
stores
the
acknowledge
status
of interrupt requests.
When an interrupt is
acknowledged, the controller selects the highest priority pending
request,
clears its IRR bit, and sets its ISR bit.
ISR bits can
be automatically cleared at the end of the acknowledge
cycle
or
on
specific
command.
The ISR can be read throught the !CSR and
ICDR.
RESET clears the IRR.
2.1.S.6
ACR · The
8-bit
Auto
Clear
Register
specifies
the
clearing
mode
for
the
ISR.
A set
ACR
bit
specifies
the
corresponding ISR bit will be automatically cleared at the end of
the
acknowledge
cycle:
and
a
cleared
ACR bit means that the
corresponding ISR bit must be cleared by the CPU through the ICSR
and
ICDR.
The ACR can be read through the ICSR and ICDR.
RESET
clears the ACR.
2.1.5.7
Mode · The
8-bit
Interrupt
Controller
Mode
Register
controls
many
controller
options.
The Mode register is loaded
through the ICSR and ICDR.
It cannot be read.
Bits 00, 02,
and
07
are
available
to the ICSR on read operations.
RESET clears
the Mode
~egister.
The bits are described in Table 2·11.
Table 2·11:
Interrupt Controller Mode Register Bits
+ . . . . . -. + . . . . . . . . . . . . -. . . . . . . . . . . . . . . . . . . . . . - - . - . -. . . . . . . . . . . . . . +
I
BITS
i DESCRIPTION
+···-··-+·················--····································+
07
MM ·· Master
~ask.
Enables
(set)
and
disables
06:05
04
(cleared) group interrupts to the CPU.
RPl:RPO ·· Repister
Preselect.
Select
the
internal
register to be read when the CPU reads the ICDR:
RPl RPO Register
0
0
ISR
0
1
IMR
1
0
IRR
1
l
ACR
REQP
Interrupt
Request
Polarity.
Determines
interrupt
request transition direction for setting IRR
bits.
Set
=
LOW
to
HIGH,
cleared
•
HIGH
to
LOW.
(Should always be cleared.)
03
GIP ·· Group Interrupt (GINT) Polarity.
When set, GINT
is
asserted
HIGH; when cleared, GINT is asserted LOW.
(Should always be cleared.)
2-11
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